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  3. AR# 46370: Xilinx 7 Series FPGA Solution Center

Xilinx 7 Series FPGA Solution Center

The 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.

Design Assistant

Xilinx 7 Series FPGA Solution Center - Design Assistant

The 7 Series FPGA Design Assistant walks you through the recommended design flow for 7 series FPGAs while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently with 7 series FPGAs.

NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


First, select the design phase for which you have a question or are troubleshooting an issue related to your 7 series FPGA design. This ensures that the Design Assistant points you to the information you need to move forward with your design.

(Xilinx Answer 46433) - Getting Started with 7 series FPGAs
(Xilinx Answer 46489) - Designing for 7 series FPGAs
(Xilinx Answer 46520) - Board Level Considerations
(Xilinx Answer 46719) - Troubleshooting - Clocking, Fabric, block RAM/FIFO

* For troubleshooting of other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.


Documentation

7 Series FPGA Documentation - What documentation should I review to find out if the 7 series FPGA features and specifications are right for my system?

What documentation should I review to find out if the 7 series FPGA features and specifications are right for my system?

NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


The 7 Series FPGA Documentation Center contains all 7 series FPGA related documentation:
http://www.xilinx.com/support/documentation/7_series.htm

The following documents are available:

  • 7 Series FPGAFamily Overview
  • Artix-7 FPGA Data Sheet: DC and Switching Characteristics
  • Kintex-7 FPGA Data Sheet: DC and Switching Characteristics
  • Virtex-7 FPGA Data Sheet: DC and Switching Characteristics
  • 7 SeriesErrata
  • 7 SeriesUser Guides

Use the7 Series Family Overview to understand the features available in the7 series FPGA device family and view the differences among the devices within the 7 series FPGA family to assist in product selection.

Use the7 Series FPGA Data Sheets to review the DC and Switching Characteristic specifications for the7 series device family.

Review the7 Series Errata to determine whether the device you are considering has any exceptions to data sheet specifications.

Review the7 Series User Guides to understand usage details for the7 series FPGA resources.


Design Advisories

Design Advisory Master Answer Record for Kintex-7 FPGA

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Kintex-7 devices and related issues that impact Kintex-7 FPGA designs.


Design Advisories Alerted on April 17th, 2017

04/17/2017(Xilinx Answer 69034) Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential IO Standards.

Design Advisories Alerted on March 28, 2016

03/28/2016(Xilinx Answer 66173)Design Advisory for Vivado 2015.4 - Vivado Timing WNS Alert - Missing Timing Arc on BUFR to BUFG clock path causes hold violations on board

Design Advisories Alerted on November 10, 2014

11/10/2014(Xilinx Answer 62631)Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs

Design Advisories Alerted on September 22, 2014

09/22/2014(Xilinx Answer 61875)Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete.

Design Advisories Alerted on June 16, 2014

06/16/2014(Xilinx Answer 60845)Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation
06/16/2014 (Xilinx Answer 59294)Design Advisory GT wizard - CPLL causes power spike on power up for 7 series Transceivers

Design Advisories Alerted on May 26, 2014

05/26/2014(Xilinx Answer 60356)Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates
05/26/2014(Xilinx Answer 45360)Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Updated the RXCDR_CFG setting for SATA Gen 2/Gen 3 and PMA_RSV for 6.6 Gbps

Design Advisory Alerted on January 20, 2014

01/20/2014(Xilinx Answer 59035)Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2

Design Advisories Alerted on November 25, 2013

11/25/2013(Xilinx Answer 58244)Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode
11/25/2013(Xilinx Answer 45360)Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver; added reference to the user guide UG476 for RX_DFE_KL_CFG2 setting

Design Advisory Alerted on October 23, 2013

10/23/2013(Xilinx Answer 51554)Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs

Design Advisory Alerted on September 16, 2013

09/16/2013(Xilinx Answer 57193)Design Advisory for the Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed

Design Advisory Alerted on August 26, 2013

08/19/2013(Xilinx Answer 57045)Design Advisory for Artix-7/Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration

Design Advisory Alerted on August 5, 2013

08/05/2013(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs

Design Advisory Alerted on May 20, 2013

05/16/2013(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs

Design Advisories Alerted on May 13, 2013

05/13/2013(Xilinx Answer 55366) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - Transceiver Wizard Sets Suboptimal RX Termination Use Modes
05/13/2013(Xilinx Answer 55791) Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5

Design Advisories Alerted on April 3, 2013

04/03/2013(Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode
04/03/2013(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices

Design Advisory Alerted on January 21, 2013

1/17/2013(Xilinx Answer 53740) Updated Design Advisory for 7-Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature.

Design Advisory Alerted on December 18, 2012

12/13/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.

Design Advisories Alerted on November 5, 2012

10/31/2012(Xilinx Answer 50617) Updated Design Advisory for Kintex-7 and Virtex-7 FPGA Production GTX Transceivers with references to specific devices; updated the bitstream compatibility section
10/25/2012(Xilinx Answer 50906) Updated Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices; updated for 14.3/2012.3 release

Design Advisories Alerted on October 29, 2012

10/25/2012(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode

Design Advisories Alerted on October 22, 2012

10/22/2012(Xilinx Answer 45360) Updated the RXCDR_CFG values in the Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver
10/22/2012(Xilinx Answer 50617) Updated the bitstream compatibility section in the Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceiver

Design Advisory Alerted on October 15, 2012

10/15/2012(Xilinx Answer 51884) Design Advisory for Kintex-7 and Virtex-7 GTX Production Silicon CDR Attribute Updates

Design Advisory Alerted on September 10, 2012

09/10/2012(Xilinx Answer 51580) Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for block Ram (BRAM) or FIFO Components for PERIOD constraint analysis

Answer Records Upgraded to Design Advisories

09/10/2012(Xilinx Answer 45781) Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option
09/10/2012(Xilinx Answer 44971) Design Advisory for 7 Series XADC - Accuracy of On Chip Reference

Design Advisory Alerted on August 20, 2012

08/17/2012(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices
08/20/2012(Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time changes in ISE 14.2 and Vivado 2012.2 release

Design Advisories Alerted on July 25, 2012

07/19/2012(Xilinx Answer 47817) Updated Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up/Power-down with additional current draw when following the recommended sequence, with information about duration of current draw, simultaneous power-up and more FAQs.
07/19/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX General ES Transceiver with RX_DFE_XYD_CFG value.
07/19/2012(Xilinx Answer 50617) Design Advisory for the Kintex-7and Virtex-7 FPGA Production GTX Transceivers.

Design Advisories Alerted on July 2, 2012

06/28/2012(Xilinx Answer 47817) Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up.
06/28/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon - Updated GTX software use mode changes (Xilinx Answer 43339) with the latest GTXE2_COMMON use model change information.

Design Advisory Alerted on May 8, 2012

05/07/2012(Xilinx Answer 47248) Design Advisory for the Kintex-7 FPGA - XC7K325T CES9937 Initial Engineering Sample (IES) Supported in ISE 13.4 only

Design Advisory Alerted on March 26, 2012

03/22/2012(Xilinx Answer 45360) Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon - Updated RXCDR_CFG setting for half-rate mode.

Design Advisory Alerted on February 27, 2012

02/23/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon to include new RXCDR_CFG settings and a link to GTX software known issues/use mode changes.

Design Advisory Alerted on January 30, 2012

01/24/2012(Xilinx Answer 45360) Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon

Design Advisory Alerted on January 16, 2012

01/10/2012(Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified

Design Advisory Alerted on November 21, 2011

11/21/2011(Xilinx Answer 44174) Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisory Alerted on October 17, 2011

10/17/2011(Xilinx Answer 44421) Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage

Design Advisory Alerted on July 6, 2011

07/06/2011(Xilinx Answer 42615) Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 design tools

Answer Number Answer Title Version Found Version Resolved
44421 Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage N/A N/A
44174 Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup N/A N/A
50906 Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT, 1140XT - Bitstream compatibility requirements between GES and Production devices N/A N/A
51580 Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for Block RAM (BRAM) or FIFO Components for PERIOD constraint analysis N/A N/A
45781 Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option N/A N/A
44971 Design Advisory for 7 Series XADC - Accuracy of On Chip Reference N/A N/A
52193 Design Advisory for 7 Series BPI Multiboot - When fallback occurs, flash access is always in BPI Asynchronous Mode N/A N/A
53740 Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature N/A N/A
55791 Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5 N/A N/A
55366 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers: Transceiver Wizard Sets Suboptimal RX Termination Use Modes N/A N/A
57045 Design Advisory for Artix-7, Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration N/A N/A
57193 Design Advisory for Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed N/A N/A
51554 Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs N/A N/A
58244 Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode N/A N/A
59035 Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2 N/A N/A
62631 Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs N/A N/A

Design Advisory Master Answer Record for Virtex-7 FPGA

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Virtex-7 FPGA and related issues which impact Virtex-7 FPGA designs.


Design Advisories Alerted on April 17th, 2017

(Xilinx Answer 69034)Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential IO Standards.

Design Advisories Alerted on March 28, 2016

(Xilinx Answer 66173)Design Advisory for Vivado 2015.4 - Vivado Timing WNS Alert - Missing Timing Arc on BUFR to BUFG clock path causes hold violations on board

Design Advisory Alerted on January 19, 2015

01/19/2015(Xilinx Answer 63110)Design Advisory for 7 Series GTH Transceiver Wizard: DFE incorrectly set to HOLD after adaptation in Vivado 2013.4 to 2014.4

Design Advisories Alerted on November 10, 2014

11/10/2014(Xilinx Answer 62631)Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs

Design Advisories Alerted on September 22, 2014

09/29/2014(Xilinx Answer 61875)Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete.

Design Advisories Alerted on September 01, 2014

09/01/2014(Xilinx Answer 61748)Design Advisory for Vivado Power/XPE - GTH - LPM/DFE mode under-reporting for MGTAVcc current in XPE.

Design Advisories Alerted on June 16, 2014

06/16/2014(Xilinx Answer 60845)Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation
06/16/2014 (Xilinx Answer 59294) - Design Advisory GT wizard - CPLL causes power spike on power up for 7 series Transceivers

Design Advisories Alerted on May 26 , 2014


05/26/2014(Xilinx Answer 60356)Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates
05/26/2014(Xilinx Answer 60489)Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier: GTH/GTP Production RX reset sequence can get stuck
05/26/2014(Xilinx Answer 45360)Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Updated the RXCDR_CFG setting for SATA Gen 2/Gen 3 and PMA_RSV for 6.6 Gbps

Design Advisory Alerted on January 20, 2014

01/20/2014(Xilinx Answer 59035)Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2

Design Advisories Alerted on November 25, 2013

11/25/2013(Xilinx Answer 58244)Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode
11/25/2013(Xilinx Answer 45360)Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver; added reference to the user guide UG476 for RX_DFE_KL_CFG2 setting

Design Advisory Alerted on October 23, 2013

10/23/2013(Xilinx Answer 51554)Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs

Design Advisory Alerted on September 16, 2013

09/16/2013(Xilinx Answer 57193)Design Advisory for the Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed

Design Advisory Alerted on August 5, 2013

08/05/2013(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs

Design Advisories Alerted on July 29, 2013

07/29/2013(Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Updated QPLL_CFG, QPLL_LOCK_CFG and QPLL_LOCK_CFG attributes
07/29/2013(Xilinx Answer 56332) Design Advisory for Virtex-7 GTH - QPLL Attribute Updates for Production Silicon: Updated QPLL_CFG, QPLL_LOCK_CFG and COMMON_CFG attributes

Design Advisory Alerted on May 20, 2013

05/16/2013(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs

Design Advisories Alerted on May 13, 2013

05/13/2013(Xilinx Answer 55366) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - Transceiver Wizard Sets Suboptimal RX Termination Use Modes
05/13/2013(Xilinx Answer 55791) Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5

Design Advisory Alerted on April 15, 2013

04/12/2013(Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Updated GTHE2_COMMON/BIAS_CFG use mode to include clock forwarding and added the RX reset sequence, TX sync controller sections

Design Advisories Alerted on April 3, 2013

04/03/2013(Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode
03/26/2013(Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Updated RX_DFE_KL_CFG setting
04/03/2013(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices

Design Advisory Alerted on March 19, 2013

03/07/2013(Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Updated LPM port settings to be in adapt mode, Changed QPLL_CFG settings from "line rate" to QPLL frequency

Design Advisory Alerted on February 25, 2013

02/21/2013(Xilinx Answer 53779) Design Advisory for Virtex-7 FPGA GTH Production Transceiver RX Reset Sequence Requirement; Updated to reflect the correct GTH mode combination where the new reset is required

Design Advisory Alerted on February 18, 2013

02/15/2013(Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Added RXCDR_CFG setting for PCIe Gen3, updated DFE port settings to be in adapt mode

Design Advisory Alerted on February 11, 2013

02/04/2013(Xilinx Answer 47128) Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon; added PCS_RSVD_ATTR[8] and note

Design Advisory Alerted on February 4, 2013

01/31/2013(Xilinx Answer 53779) Design Advisory for Virtex-7 FPGA GTH Transceiver: RX Reset Sequence Requirement for Production Silicon

Design Advisory Alerted on January 21, 2013

01/17/2013(Xilinx Answer 53740) Updated Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature.

Design Advisories Alerted on January 14, 2013

01/09/2013(Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: updated BIAS_CFG, QPLL_CFG settings and added QPLL_CLKOUT_CFG to the table.

Design Advisories Alerted on December 18, 2012

12/13/2012(Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.
12/13/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.

Design Advisory Alerted on November 13, 2012

11/09/2012(Xilinx Answer 47443) Updated Table 1 in the Design Advisory for the Virtex-7 GTH Transceiver Power-up/Power-down to include all devices and packages

Design Advisories Alerted on November 5, 2012

10/31/2012(Xilinx Answer 50617) Updated Design Advisory for Kintex-7 and Virtex-7 FPGA Production GTX Transceivers with references to specific devices; updated the bitstream compatibility section
10/25/2012(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode
10/25/2012(Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues and Work-arounds for General Engineering Sample (ES) Silicon; added RXCDR_CFG values for 8B/10B

Design Advisories Alerted on October 18, 2012

10/17/2012(Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues and Work-arounds for General Engineering Sample (ES) Silicon
10/17/2012(Xilinx Answer 51884) Design Advisory for Kintex-7 and Virtex-7 FPGA GTX Production Silicon CDR Attribute Updates
10/17/2012(Xilinx Answer 47128) Updated Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon; added the ACJTAG use mode

Design Advisory Alerted on September 10, 2012

09/10/2012(Xilinx Answer 51580) Design Advisory for 14.1/14.2 Timing Analysis 7 Series FPGA - Clock Arrival Times are Incorrect for Block Ram (BRAM) or FIFO Components for PERIOD constraint analysis

Answer Records Upgraded to Design Advisory

09/10/2012(Xilinx Answer 45781) Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option
09/10/2012(Xilinx Answer 44971) Design Advisory for 7 Series XADC - Accuracy of On Chip Reference

Design Advisories Alerted on August 20, 2012

08/20/2012(Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite releases
08/17/2012(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices
08/17/2012(Xilinx Answer 47443) Updated Design Advisory for the Virtex-7 GTH Transceiver Power-up/Power-down with updated VMGTAVTT additional current draw value

Design Advisory Alerted on August 13, 2012

08/10/2012(Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver with example GTHE2_COMMON instantiations on the GTHE2_COMMON/BIAS_CFG section and added some references to ISE 14.2/Vivado 2012.2 in general.

Design Advisory Alerted on July 30, 2012

07/27/2012(Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver that there is no issue with GTH Resistor Calibration and no work-around is required.

Design Advisories Alerted on July 25, 2012

07/19/2012(Xilinx Answer 47443) Updated Design Advisory for the Virtex-7 GTH Transceiver Power-up/Power-down with information about duration of current draw, simultaneous power-up and more FAQs.
07/19/2012(Xilinx Answer 47817) Updated Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up/Power-down with additional current draw when following the recommended sequence, information about duration of current draw, simultaneous power-up and more FAQs.
07/19/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX General ES Transceiver with RX_DFE_XYD_CFG value.
07/19/2012(Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers.

Design Advisory Alerted on July 16, 2012

07/12/2012(Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver with updated QPLL_CFG and QPLL_LOCK_CFG values and GTH Transceiver Link Margin Reduction section.

Design Advisories Alerted on July 2, 2012

06/28/2012(Xilinx Answer 47817) Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up.
06/28/2012(Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver to include latest PMA_RSV2, RX_BIAS_CFG, RXDFEXYDEN values in the attributes and ports section.
06/28/2012(Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon.

Design Advisory Alerted on June 11, 2012

06/08/2012(Xilinx Answer 47443) Updated the Design Advisory for 7 series FPGAs GTH Transceiver Power up.

Design Advisory Alerted on May 28, 2012

05/24/2012(Xilinx Answer 47128) Updated Design Advisory to include GTHE2_COMMON and termination use modes, the Initial ES errata items section, and updated the resistor calibration section.

Design Advisory Alerted on May 15, 2012

05/14/2012(Xilinx Answer 47128) Updated Design Advisory title to "Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon" and included the Resistor Calibration section and updated BIAS_CFG setting

Design Advisories Alerted on May 8, 2012

05/03/2012(Xilinx Answer 47128) Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon
05/03/2012(Xilinx Answer 47443) Design Advisory for 7 series FPGAs GTH Transceiver - Static Power Errata

Design Advisory Alerted on April 30, 2012

4/30/2012(Xilinx Answer 47342) Design Advisory for Virtex-7 GTH Serial Transceiver Package Diagram corrections

Design Advisory Alerted on January 16, 2012

01/10/2012(Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified

Design Advisory Alerted on November 21, 2011

11/21/2011(Xilinx Answer 44174) Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisory Alerted on July 6, 2011

07/06/2011(Xilinx Answer 42615) Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Design Suite

Answer Number Answer Title Version Found Version Resolved
44174 Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup N/A N/A
50906 Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT, 1140XT - Bitstream compatibility requirements between GES and Production devices N/A N/A
51296 Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases N/A N/A
51580 Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for Block RAM (BRAM) or FIFO Components for PERIOD constraint analysis N/A N/A
45781 Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option N/A N/A
44971 Design Advisory for 7 Series XADC - Accuracy of On Chip Reference N/A N/A
55791 Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5 N/A N/A
55366 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers: Transceiver Wizard Sets Suboptimal RX Termination Use Modes N/A N/A
57193 Design Advisory for Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed N/A N/A
51554 Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs N/A N/A
58244 Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode N/A N/A
59035 Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2 N/A N/A
62631 Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs N/A N/A
66788 Design Advisory for MIG 7 Series DDR3 - DQS_BIAS is not properly enabled for HR banks causing potential calibration failures N/A N/A

Top Issues

Xilinx 7 Series FPGA Solution Center - Top Issues

The following answer records cover current known issues related to 7 series FPGAs.

NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to the 7 series FPGAs.

(Xilinx Answer 40905) - Click here to view 7 Series FPGA answer records related to common questions or known issues
(Xilinx Answer 43347) - Click here to view the Kintex-7 Initial Engineering Samples Known Issues Master Answer Record
(Xilinx Answer 45696) - Click here to view the Kintex-7 General Engineering Samples Known Issues Master Answer Record
(Xilinx Answer 43423) - Click here to view the Virtex-7 Initial Engineering Samples Known Issues Master Answer Record
(Xilinx Answer 46345) - Click here to view the Virtex-7 485T General Engineering Samples Known Issues Master Answer record
Answer Number Answer Title Version Found Version Resolved
40905 7 Series - ISE 13.x Software Known Issues related to the 7 Series FPGAs N/A N/A
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A
45696 Kintex-7 - General Engineering Sample (ES) Known Issues Master Answer Record N/A N/A
43423 Virtex-7 Initial ES Known Issues Master Answer Record N/A N/A
46345 Virtex-7 485T General ES - Known Issues Master Answer Record N/A N/A
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