AR# 46384


Targeting KC705/VC707 for SGMII with the TEMAC and SGMII Core on Kintex-7/Virtex-7 Devices


The two ZIP files (attached at the end of this answer record) connect the v5.2 TEMAC example design targeting the KC705 board to the v11.2 1000BASE-X PCS/PMA or SGMII core to provide an example of using the SGMII interface with the Marvell PHY on the KC705 and VC707 boards.

The TEMAC is still set up to connect via MDIO to the Marvell PHY. The SGMII core was generated without an MDIO interface and it is configured via a configuration vector while the status is reported with a status vector.

For more details on the example design functionality, see "Detailed Example Design" -> "Targeting the Example Design to a Board" section in of the Tri-Mode Ethernet MAC User Guide (UG777):


Following is a general summary of the changes that were made to connect the two cores together:

  1. In the top level tri_mode_eth_mac_v5_2_example_design.v, the following modifications were made:
    1. Instantiated the gig_eth_pcs_pma_v11_2_block and connected the GMII interface to the Tri-Mode Ethernet MAC.
    2. Changed the tri_mode_eth_mac_v5_2_block instantiation to use the internal GMII interface instead of an external GMII interface (the KC705 board is only targeted if you select external GMII or RGMII interface when generating the TEMAC, so the external GMII interface was used for the top level example design and the UCF starting point).
    3. Added the correct MMCM clocking from the gig_eth_pcs_pma_v11_2_example_design.v and changed the TEMAC to be clocked by this clock.
    4. Set Configuration vector to enable AN, disable Isolate, Loopback and PowerDown.
    5. Set the Link Timer to SGMII standard.

  2. In the UCF, the following changes were made:
    1. Updated the UCF; see (Xilinx Answer 45527), to obtain the needed changes for the KC705 board revC.
    2. Added UCF constraints for the serial clock.
    3. Updated the timing and period constraints to the new clocking.
    4. Added constraints for the Synchronization and Link Status signals from the PCS/PMA core to bring these signals out to LEDs.

  3. Updated the transceiver wrappers; see (Xilinx Answer 46123).

  4. Changed the name of the reset_sync block for the pcs/pma core as both cores use a block with the same name but different ports.
AR# 46384
Date 07/06/2012
Status Active
Type General Article
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