AR# 46391


7 Series MIG v1.4 - reset_n can be moved to any bank as long as timing is met


The MIG GUI prevents the reset_n signal from being placed outside of the banks containing the memory interface (i.e. into another column). Since this signal is asynchronous, there are no FPGA limitations as to why this cannot be placed in an arbitrary bank as long as the routed design meets timing.


The current restriction is in place based on of what has been characterized. We cannot add every pin as an option in the GUI because we do not have testing scripts to verify timing is met at every single location across all MIG configurations. As long as normal FPGA timing is met, itis safe to move the reset_n signal to any bank in any column.
AR# 46391
Date 12/15/2012
Status Active
Type General Article
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