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AR# 4641

Synplify - How do I instantiate JTAG pins (TDI, TDO, TCK, TMS) in HDL as general I/O?

Description

Keywords: TDI, TDO, TCK, TMS, VHDL, Verilog, Synplify, XC4000, XC5200

Urgency: Standard

General Description:
How do I instantiate the mode pins (TDI, TDO, TCK,TMS) for Synplicity's Synplify?

Solution

1

You can instantiate the JTAG pin cells by using the Xilinx family library supplied with Synplify. Please see (Xilinx Answer 244) for details of instantiating Xilinx-specific cells.

NOTE: Please see (Xilinx Answer 2805) for information on instantiating BSCAN in HDL.

After configuration, if boundary scan is not used, the TMS, TCK, and TDI pads are unrestricted and can be used as user I/O pads, and the TDO pad can be used as a bidirectional 3-state I/O pad. Please see (Xilinx Answer 1356) for details.

Also, this functionality is only valid in the 4000E/X, Spartan, and 5200 FPGA families.

NOTE: The ports are not listed in the top-level port list.

JTAG Pins, using VHDL code

library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;

entity jtag_pins is
port ( din, clk : in STD_LOGIC;
qout : out STD_LOGIC);
end jtag_pins;

architecture xilinx of jtag_pins is

attribute black_box : boolean;

component TDI
port (I : out STD_LOGIC);
end component;

component TCK
port (I : out STD_LOGIC);
end component;

component TMS
port (I : out STD_LOGIC);
end component;

component TDO
port (O : in STD_LOGIC);
end component;

component IBUF
port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;

component OBUF
port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;

signal TCK_I, TDI_I, TMS_I, TDO_I : STD_LOGIC;
signal TCK_O, TDI_O, TMS_O, TDO_O : STD_LOGIC;

begin

U1 : TDI port map (I => TDI_I);
U2 : TCK port map (I => TCK_I);
U3 : TMS port map (I => TMS_I);
U4 : TDO port map (O => TDO_O);
U5 : IBUF port map (I => TDI_I, O => TDI_O);
U6 : IBUF port map (I => TCK_I, O => TCK_O);
U7 : IBUF port map (I => TMS_I, O => TMS_O);
U8 : OBUF port map (I => TDO_I, O => TDO_O);

-- User application insert here
process (clk)
begin
if (clk'event and clk = '1') then
qout <= TDI_O xor TCK_O xor TMS_O;
end if;
end process;

TDO_I <= din;

end xilinx;

2

JTAG pins, using Verilog code

`include "/products/synplify/lib/xilinx/xc4000.v"

module jtag_pins (din, clk, qout);
input din, clk;
output qout;

reg qout;

wire TCK_I, TDI_I, TMS_I, TDO_I;
wire TCK_O, TDI_O, TMS_O, TDO_O;

TDI U1 (.I (TDI_I));
TCK U2 (.I (TCK_I));
TMS U3 (.I (TMS_I));
TDO U4 (.O (TDO_O));
IBUF U5 (.I (TDI_I), .O (TDI_O));
IBUF U6 (.I (TCK_I), .O (TCK_O));
IBUF U7 (.I (TMS_I), .O (TMS_O));
OBUF U8 (.I (TDO_I), .O (TDO_O));

-- User application insert here
always @(posedge clk)
qout <= TDI_O ^ TCK_O ^ TMS_O;

assign TDO_I = din;

endmodule

3

Synplicity's xc4000.v library defines TDI, TCK and TMS as input pins. However, these three pins (TDI, TCK and TMS) can be configured as either input or output in XC4000/XC4000X/Spartan/Spartan-XL devices.

The following steps illustrate the configuration of any of the three pins as an output in Verilog:

1. Copy xc4000.v from <path_to_synplicity>/lib/xilinx to your project library.
2. To change TDI to an output pin, modify the module declaration as follows:

module TDI(I)/*synthesis syn_black_box*/;
input I /*synthesis .ispad=1*/;
endmodule

NOTE: Notice that the direction of port I is changed from "output" to "input".

3. Perform the same modification for other pins, if necessary.
4. Instantiate the pins in your design as illustrated in the previous Verilog example.

NOTE: Since TDI is now an output pin, it should be connected to an OBUF.

5. Include xc4000.v in your project file list and synthesize it with the other Verilog project files. Alternatively, the `include directive can be used to include the modified xc4000.v.

4

Synplicity's xc4000.vhd library defines TDI, TCK and TMS as input pins. However, these three pins (TDI, TCK and TMS) can be configured as either input or output in XC4000/XC4000X/Spartan/Spartan-XL devices.

The following steps illustrate the configuration of any of the three pins as an output in VHDL:

1. Copy xc4000.vhd from <path_to_synplicity>/lib/xilinx to your project library.
2. To change TDI to an output pin, modify the component declaration as follows:

component TDI
port( I: in STD_LOGIC);
end component;
attribute synthesis_noprune of TDI: component is true;

NOTE: The direction of port I is changed from "out" to "in", and the "synthesis_noprune" attribute is used for the component.

3. Perform the same modification for other pins if needed.
4. Instantiate the pins in your design as illustrated in the previous VHDL example.

NOTE: As TDI is now an output pin, it should be connected to an OBUF.

5. Replace "xc4000" with "work". This is because xc4000.vhd will now be compiled into a "work" library. The library declaration should appear as follows:

library work;
use work.components.all;

6. Remove TDI's (or other pins') component declaration from design file.
7. Include xc4000.vhd in your project file list and synthesize it with the other VHDL project files.
AR# 4641
Date Created 08/21/2007
Last Updated 12/16/2002
Status Active
Type General Article