2. Support
  3. AR# 4642: M1.5,bufg,vhdl: Logic trimmed when all buffers instantiated rather than placed by Express.
  4. AR# 46426: ChipScope Pro - Inserting ChipScope cores in the PlanAhead tool generates unconnected ports

AR# 46426

ChipScope Pro - Inserting ChipScope cores in the PlanAhead tool generates unconnected ports

Description


Inserting ChipScope cores in the PlanAhead tool generates unconnected ports in the 13.3 and 13.4 design tools. BitGen displays DRC errors similar to the following when this occurs:

"ERROR:PhysDesignRules:10 - The network <xxxx_cs_ila_0_0> is completely unrouted."

Solution

To avoid this issue, add KEEP attributes to the nets reported in the BitGen DRC, and run again through XST and implementation.
AR# 46426
Date 05/07/2012
Status Active
Type General Article
Tools