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AR# 4644

FPGA Express: CONV_STD_LOGIC_VECTOR converts integers to signed values only (HDL-71)

Description

Keywords: FPGA Express, Synopsys, CONV_STD_LOGIC_VECTOR, HDL-71, overflow

Urgency: Standard

General Description:
When sending an integer as the argument to the CONV_STD_LOGIC_VECTOR function found in the STD_LOGIC_ARITH package, Express assumes that the resulting STD_LOGIC_VECTOR will always be a signed number. In the follow example, the number 20 will be converted to 010100, not just 10100, and since a five bit signed vector has a range from 15 to -16, Express does not allow 20 as an input when the second input to the function is 5.

<PRE>
SIGNAL SYNC_DELAY : STD_LOGIC_VECTOR(4 downto 0);
CONSTANT DELAY : INTEGER := 20;
...
SYNC_DELAY <= CONV_STD_LOGIC_VECTOR(DELAY,5);
</PRE>

The following error will result:

Error: Constant value 20 overflowed 'sized_int:range -16 to 15'
in routine SYN_INTEGER_TO_SIGNED
called from DELAY_COUNT20 line 37 in file 'convtest.vhd' (HDL-71)

Solution

Use a temporary vector that is one bit larger than the final vector. Assign the conversion to this vector, then assign all but the MSB to the final vector.


SIGNAL SYNC_DELAY : STD_LOGIC_VECTOR(4 downto 0);
SIGNAL temp : STD_LOGIC_VECTOR(5 downto 0);
CONSTANT DELAY : INTEGER := 20;
...
temp <= CONV_STD_LOGIC_VECTOR(DELAY,6); --don't forget to increment the size by 1
SYNC_DELAY <= temp(4 downto 0);
AR# 4644
Date 08/11/2003
Status Archive
Type General Article