Description

MIG 7 Series v1.4 only allows the "PHY to Controller Clock Ratio" option to be set to 2:1 when the frequency range is set between the following (which corresponds to the device speed grade):

-1 400 MHz
-2 400-533 MHz
-3 400-533 MHz

This is incorrect.

The user should be allowed to select 2:1 mode for frequencies less than 400 MHz.

Solution

This will be fixed in the ISE 14.1 release, but you can work around this issue by manually setting the top-level parameter "nCK_PER_CLK," as long as you adhere to the frequency restrictions above.

Workaround:

Generate the design you need in 4:1 mode. 

Then, open the top-level example_top.v or <user_design>.v and change the following parameter:

CK_PER_CLK = 2

This changes the memory controller clock to DRAM clock ratio from 4 to 2.