AR# 46506


7 Series FPGA Design Assistant - Designing configurable logic structures in 7 series FPGAs


This answer record provides guidance and information on what you should know about FPGA fabric configuration and setup for 7 series FPGAs.

NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


When coding for a 7 series FPGA designs, you should follow the coding guidelines shown in the language templates and also the recommendations for coding practices discussed in the HDL Coding Practices to Accelerate Design Performance White Paper (WP231):

Follow the recommendations mentioned inthe HDL Coding Practices to Accelerate Design Performance White Paper (WP231) so that the software tools optimally utilize the FPGA fabric. You can also refer to the following answer records for more information on coding methods that can help optimize performance and reduce the amount of logic used in a design:

(Xilinx Answer 46509) - Utilizing distributed memory in fabric
(Xilinx Answer 46510) - Setting logic controls in the fabric
(Xilinx Answer 46511) - Using SRLs to conserve resources
(Xilinx Answer 46512) - Using optimization features from third-party synthesis tools

In addition, the7-Series FPGAs Configurable Logic Block User Guide (UG474) describes the primitives and blocks in more detail so that you have a better understanding of how the7 series FPGA fabric can work for you in a design:

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AR# 46506
Date 12/15/2012
Status Active
Type General Article
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