There was an issue where the SPI controller, when set up for automatic slave select assertion (SPICR register bit 7 is 0) and the SS_O port was 32-bits wide, the user would see incorrect data (bit-swapped) out on SS_O.
An endian-swap was introduced in core 1.02.a, which fixed the above issue, but also would change the endianness of the ChipSelect (CS) pins out of the core. If you set the parameterC_NUM_SS_BITS to a number other than 1, the CS pins will be endian-swapped. Please take this into consideration when designing your project.
For any further questions, please open a WebCase with Xilinx Technical Support.