This answer record provides an explanation on using flip-flop and logic controls that can be set to help improve performance of your design.
NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
There are many primitives in the 7 series FPGA fabric that can be used with Set/Reset control, clock enables, and other logic control functions. These types of logic control can either be inferred in your logic or instantiated manually.
For clocks in your design, you should always use clock enables when available in order to save your clock resources, improve timing characteristics, and reduce power. If you want to enable a clock on an entire clock tree, you can use the clock enable available on BUFGs. If only registers need to be enabled, use the individual clock enable controls that are available in the registers.
When using a set or reset function in your design, always use the set or reset synchronously. Using an asynchronous reset can result in degraded performance as the synthesis tools cannot perform optimizations as easily. For other control ports used in different primitives, synchronous control should be used for the same reason since asynchronous operation limits optimization during synthesis.
Please read over the HDL Coding Practices to Accelerate Design Performance White Paper (WP231) as it discusses in detail coding practices that should be used to optimize performance with your design: http://www.xilinx.com/support/documentation/white_papers/wp231.pdf
In addition, the7 series FPGAUser Guides describe the primitives and blocks (block RAM, CLB, MMCM, buffers, etc.) in more detail so that you have a better understanding of how the 7 series FPGA fabric can work for you in a design.