The following Answer Record points you to information on how to infer block RAM and FIFO primitives in your HDL code.
Note: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370).
The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices.
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Block RAMs and FIFOs can be inferred if implemented correctly in your HDL code.
The XST User Guide (UG627) discusses in detail how you need to code in order to infer a block RAM or FIFO in your design:
https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug953-vivado-7series-libraries.pdf
In addition, the HDL Coding Practices to Accelerate Design Performance White Paper (WP231) provides additional information on coding techniques that can be used to optimize performance of Block RAM in your design.
Refer to the "Maximize Block RAM performance" section:
https://www.xilinx.com/support/documentation/white_papers/wp231.pdf
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46517 | 7 Series FPGA Design Assistant - Designing for I/O, PCIe, EMAC, DSP, and XADC in 7 Series FPGAs | N/A | N/A |
| AR# 46515 | |
|---|---|
| Date | 11/15/2017 |
| Status | Active |
| Type | Solution Center |
| Devices | |