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AR# 46516

7 Series FPGA Design Assistant - Using block RAM CORE Generator and FIFO CORE Generator to set up the blocks for use in HDL code


This Answer Record provides information on how to set up block RAM or FIFOs with IP generated CORE Generator software.
NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


If you need to directly instantiate a block RAM or FIFO block directly into your design, the CORE Generator tool can be used. For more information on how to use the block RAM Generator or FIFO Generator IP cores, refer to the corresponding data sheets listed below for each IP core:
Once you generate either of these cores in the CORE Generator tool, the cores include an instantiation template (.veo file for Verilog, .vho file for VHDL) that you can use to instantiate the core into your HDL code.

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AR# 46516
Date 11/10/2014
Status Active
Type General Article
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