AR# 46517

7 Series FPGA Design Assistant - Designing for I/O, PCIe, EMAC, DSP, and XADC in 7 Series FPGAs

Description

The following answer record points you to the information required for designing an I/O interface, PCIe, EMAC, DSP and XADC in 7 Series FPGAs.

NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.

Solution

Please refer to the following Solution Center Answer Records and User Guides which provide more information when designing for a I/O interface, PCIe, EMAC, DSP, or XADC design.

(Xilinx Answer 37181) - High-Speed Serial I/O Solution Center
(Xilinx Answer 34536) - PCIe Solution Center
(Xilinx Answer 38279) - Ethernet IP Solution Center
7-Series FPGAsDSP48E1 Slice User Guide (UG479):
http://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf
7-SeriesFPGAsXADC User Guide (UG480):
http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf

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Linked Answer Records

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
46504	7 Series FPGA Design Assistant - Information about the Clocking Wizard	N/A	N/A
46505	7 Series FPGA Design Assistant - Details on using different clocking buffers	N/A	N/A
46509	7 Series FPGA Design Assistant - Utilizing distributed memory in fabric	N/A	N/A
46510	7 Series FPGA Design Assistant - Setting logic controls in the fabric	N/A	N/A
46511	7 Series FPGA Design Assistant - Using SRLs to conserve resources	N/A	N/A
46512	7 Series FPGA Design Assistant - Using optimization features from third-party synthesis tools	N/A	N/A
46515	7 Series FPGA Design Assistant - How to infer the use of Block RAM and FIFO primitives in your HDL code	N/A	N/A
46516	7 Series FPGA Design Assistant - Using block RAM CORE Generator and FIFO CORE Generator to set up the blocks for use in HDL code	N/A	N/A
38279	Ethernet IP Solution Center	N/A	N/A
46489	7 Series FPGA Design Assistant - Designing for 7 series FPGAs	N/A	N/A
37181	Xilinx High-Speed Serial I/O Solution Center	N/A	N/A

AR# 46517
Date	02/07/2013
Status	Active
Type	General Article
Devices	Artix-7 Kintex-7 Virtex-7

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