AR# 46535
KC705 User Guide (UG810) - GPIO_DIP_SW0 pinout incorrect in Table 1-24
Description
In Table 1-24 of the KC705 Evaluation Board for the Kintex-7 FPGA User Guide v1.0 (UG810), the FPGA pin for GPIO_DIP_SW0 is listed as AB25. However, the schematic and the UCF for the KC705 lists the FPGA pin for GPIO_DIP_SW0 as Y29.
Which is the correct FPGA pin for GPIO_DIP_SW0?
Solution
The schematic and the UCF are correct; GPIO_DIP_SW0 is connected to FPGA pin Y29 on the Kintex-7 device.
Table 1-26 of the KC705 Evaluation Board for the Kintex-7 FPGA User Guide v1.1 (UG810) has been updated to reflect the correct FPGA connection.
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Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45934 | Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45934 | Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| AR# 46535 | |
|---|---|
| Date | 01/10/2014 |
| Status | Active |
| Type | General Article |
| Boards & Kits |
|