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AR# 46616

13.4 Virtex-6 GTH IBERT - Core does not meeting timing


If I generate a Virtex-6 FPGAGTH IBERT design in 13.4, implementation fails due to timing issues.


This is a known issue in 13.4 for the Virtex-6 GTH IBERT core.The XST synthesis max fanout is set to 2 for generating theIBERT core which causes the tools to replicate resources, makingit difficult for the tools to meet timing with the core.This issue will be fixed in ISE Design Suite 14.1.

To work around this issue, edit the tcl file (custom_targets.tcl) located at the directory below. Remove line 97"setXSTOption max_fanout2," save, exit, and re-generate the IBERT core (note that you should close Xilinx software tools prior to changing the tcl script).


If the IBERT core still does not meet timing, refer to (Xilinx Answer 44849) for some recommendations that you can try to help the core meet timing.

AR# 46616
Date 05/19/2012
Status Archive
Type Known Issues
  • Virtex-6 HXT
  • ChipScope Pro - 13.4
  • ChipScope Pro IBERT for Virtex-6 GTH
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