The AXI MM Bridge for PCIe is designed to hold off sending Memory Read TLPs when a configuration TLP is sent. This is done so that the bridge can safely assume the returned completion is for the configuration request, which makes routing the completions less timing intensive. However, under some conditions, if configurationrequest TLPs are pending and read request is being received from the AXI interface, a memory read TLP is incorrectly transmitted while the configuration completion is still outstanding. While this is compliant from a PCI Express perspective, the bridge is not designed to handle this scenario.
The result is that the completions with data for the memory read request will be routed incorrectly and purged internally in the AXI MM bridge, and not returned to the AXI interface.
This issue is fixed in v1.03a, which will be released in ISE 14.1 software.Prior to ISE 14.1 release, if this issue is a concern, please open a case with Xilinx support and refer to this answer record. To work around this issue, do not send read request from the AXI side until all configuration requests to enumerate and configure the link partner device are completed.
Revision History 03/05/2012 - Initial Release
NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.