AR# 46647

AXI Bridge for PCI Express - zero-length write transactions on the AXI Slave port cause the AXI interface to hang

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969).

A zero-length write transaction on the AXI Slave port of the AXI Bridge for PCI Express will cause the AXI interface to stall by deasserting either a wread or wready of the Write Address or Write Data Channel, respectively.

Solution

To work around this issue, avoid mastering on the AXI Slave Write Channel with a zero-length write transaction.

A fix for this issue is not yet available, but is being investigated. If this issue is a concern, please open a case with Xilinx support and refer to this answer record.

Revision History

03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
44969	AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
44969	AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7	N/A	N/A

AR# 46647
Date	12/15/2012
Status	Active
Type	General Article
IP	AXI PCI Express (PCIe)

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