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  3. AR# 46681: MIG Spartan-6 MCB - User Interface - Why are the pX_wr_full and pX_wr_empty UI signals held high during intialization?

AR# 46681

MIG Spartan-6 MCB - User Interface - Why are the pX_wr_full and pX_wr_empty UI signals held high during intialization?

Description

After reset and throughout initialization and calibration, the MIG Spartan-6 MCB user interface signals "px_wr_full"and "px_wr_empty" are both held high while "wr_count" is all zeros. This is not standard FIFO design where the full flag would be low while the count value is 0. This answer record details this expected behavior.


Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The Spartan-6 MIG design holds "px_wr_full" high during calibration to prevent data to from being written into the FIFO. Once calibration completes, "calib_done" asserts, px_wr_full will be brought low and normal operation writes and reads can be requested from the user interface.


For more information on the MCB User Interface signals, please see:
(Xilinx Answer 43322) MIG Spartan-6 MCB - User Interface - Signals and Parameter Descriptions

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43322 MIG Spartan-6 MCB - User Interface - Signals and Parameter Descriptions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43322 MIG Spartan-6 MCB - User Interface - Signals and Parameter Descriptions N/A N/A
AR# 46681
Date 02/18/2013
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
IP
  • MIG Virtex-6 and Spartan-6
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