The PlanAhead tool projects can contain multiple "synth_##", and under each synthesis run one can have multiple "impl_##" runs as well. Modifications made in the netlist design of one "synth_##" run should not affect "impl_##" of another "synth_##" run.
For example, the project looks as follows:
If the ChipScope tool is added into the synth_1 netlist design, then impl_1 and impl_2 should contain the ChipScope tool. However, impl_3 and impl_4 should not. This is not the case, the impl_3/_4/_5 and _6 all see the ChipScope tool included.
Why does this happen?
The PlanAhead tool has not been programmed to support this flow correctly. This functionality will be supported in the Vivado tool.
To work around this issue in the PlanAhead tool, use separate projects as opposed to multiple synthesis runs.