AR# 46720


7 Series FPGA Design Assistant - Troubleshooting common clocking problems


The Answer Record helps guide you to solutions to common problems with Clocking in7 Series FPGA designs.

NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


Whether the issue you are having relates to issues with achieving lock, or you are experiencing more jitter on your output clock than expected, this answer record can help find a solution.

The following suggestions below should always be verified with any clocking design:

Verify MMCM/PLL is operating within data sheet limits

Verify that the MMCM/PLL is operating within the 7 Series data sheet limits. Find the MMCM or PLL specifications in the appropriate 7 Series data sheet, which can be found at the following location:

It is very important that the input clock specifications, VCO frequency, and output specifications are within the data sheet limits. Operating outside of these limits can cause unexpected behavior and may cause the PLL/MMCM to not function at all.

Verify amount of jitter on the input clock

The MMCM and PLL have maximum limits on the allowed jitter on the input clock. This information is also in the data sheets. Always check the data sheet specifications on jitter given by your oscillator manufacturer and verify this number using an oscilloscope. When making the measurements, it is very important to make sure that you are using an appropriate oscilloscope and probe typeto make accurate measurements. Always measure at the pin of the FPGA (or as close to the pin as possible if your board design does not allow this).

Use the Clocking Wizard to estimate output clock jitter

The Clocking Wizard can be used to generate MMCM/PLL clocking configurations. It is available in CORE Generator. The wizard will also estimate the amount of jitter to expect on the output clock in this system. Note that this is an estimate only, and actual values may be greater or less than this value. Also, keep in mind that if a design has a lot of switching happening, this can cause more output jitter on the clock.

Below are a list of recommendations that you can try which may help debug common clocking issues:

Setting the bandwidth attribute to an appropriate option

If a low jitter output clock is necessary from the MMCM/PLL, use a BANDWIDTH setting of LOW. This will reduce the amount of jitter on the output clock, but will increase the static offset of the output clocks for the MMCM/PLL. If the amount of jitter on the output clock is not as important to the system, set this to OPTIMIZED.

Probe FPGA power supplies

The MMCM/PLL are both powered off of the VCCAUX supply of the FPGA. If the FPGA power supplies are noisy, this can cause issues with functionality in the FPGA. Take scope shots of the VCCINT, VCCAUX, and GND planes and monitor if there is voltage noise on the power planes. If there is a lot of noise on the supplies, verify that the recommendations for decoupling power supplies are followed. These recommendations are provided in the 7 Series FPGA PCB Design and Pin Planning User Guide:

Try running a testcase which contains only the MMCM/PLL design

It is usually a good idea to isolate parts of a design to verify that the core functionality of a specific part works. If the MMCM/PLL only work properly when the design is isolated to only the MMCM/PLL, then something else could be causing the issue. With the reduced design, you should monitor the power planes and output clocks using a scope to see if the behavior changes. If the amount of noise/jitter on the output clocks/power planes are significantly better with the reduced design, then you can conclude that something in your design is causing the issue. Here are some things to try which may help:

  • Check the Simultaneous Switching Outputs (SSO) numbers in your design and make surethey arenot violating our recommendations
  • Try moving the MMCM/PLL to a different location away from intensive fabric switching
  • If a large portion of your design is clocked on the same clock edge, this can cause spikes in the power or ground plane due to an instantaneous current draw. Try moving some portions of your design to phase shifted clocks to more evenly distribute current demand in the design
  • Improve board level power decoupling to help reduce noise on the power supplies

If you still have a problem after running through the suggestions, open a WebCase with Xilinx Technical Support:

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46719 7 Series FPGA Design Assistant - Troubleshooting N/A N/A
AR# 46720
Date 01/25/2013
Status Active
Type General Article
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