UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46743

Would Vivado Synthesis be able to infer tristate logic in a lower level module when flatten_hierarchy is set to none?

Description

Would Vivado Synthesis be able to infer tristate logic in a lower level module when flatten_hierarchy is set to none?

Solution

When the -flatten_hierarchy switch is set to "none," it is not recommended to have tristate at lower level.

In case of a design containing tristate logic, setting flatten_hierarchy to "none" does not actually force the design to preserve hierarchy. 

Vivado synthesis automatically flattens the hierarchy before the I/O insertion stage while trying to infer a tristate primitive for a tristate logic in a lower level module and then rebuild the hierarchy.

The workaround would be either setting -flatten_hierarchy to "full" or "rebuilt" or move the tristate logic to top level in the HDL code.

AR# 46743
Date Created 10/08/2012
Last Updated 04/16/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite