The Spartan-6 clocking structure is made up of CMT tileseach containing twoDigital Clock Managers (DCMs) andone Phase Locked Loop (PLL). There are also different buffer types for routing clocks throughout the device. This Answer Record contains information on designing clocking structures for Spartan-6 FPGAs.
NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.
PLL ThePhase Locked Loop(PLL) available in the Spartan-6 device family allows you to perform the following:
Clock Frequency Synthesis
Phase Alignment/Phase Shifting
Cleaning up a noisy clock (jitter filter)
The Digital Clock Managers (DCMs) in Spartan-6 provide advanced clocking capabilities including the following:
Eliminate input clock skew
Phase shift clock outputs
Multiply and divide the input clock to synthesize a new clock frequency
When using thePLL or DCMin your design, Xilinx recommends that you use the Clocking Wizard, available in the CORE Generator software, to help you generate yourPLL or DCMbased on your needs using an easy to use Wizard.For more information about this Wizard, including how to access the Clocking Wizard,see (Xilinx Answer 46749).
Clock Buffers Spartan-6 provides multipleoptions for buffers that you can use inside your device depending on application. Some are specialized for I/O interfaces, while others are better suited for global clock distribution inside of the FPGA.For additional information on the types of buffers available in the Spartan-6 family, refer to (Xilinx Answer 46750).