DCM
The Digital Clock Managers (DCMs) in Spartan-6 provide advanced clocking capabilities including the following:
When using thePLL or DCMin your design, Xilinx recommends that you use the Clocking Wizard, available in the CORE Generator software, to help you generate yourPLL or DCMbased on your needs using an easy to use Wizard.For more information about this Wizard, including how to access the Clocking Wizard,see (Xilinx Answer 46749).
Clock Buffers
Spartan-6 provides multipleoptions for buffers that you can use inside your device depending on application. Some are specialized for I/O interfaces, while others are better suited for global clock distribution inside of the FPGA.For additional information on the types of buffers available in the Spartan-6 family, refer to (Xilinx Answer 46750).
Answer Number | Answer Title | Version Found | Version Resolved |
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44744 | Spartan-6 FPGA Solution Center | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
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46749 | Spartan-6 FPGA Design Assistant - Information about the Clocking Wizard | N/A | N/A |
46739 | Spartan-6 FPGA Design Assistant - Designing for a Spartan-6 FPGA | N/A | N/A |
46750 | Spartan-6 FPGA Design Assistant - Details on using different clocking buffers | N/A | N/A |
AR# 46744 | |
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Date | 12/15/2012 |
Status | Active |
Type | General Article |
Devices |