I am attempting to simulate a single-cascade mode SDA FIR filter; however, when I generate the single FIR filter in cascade mode, data is fed into the SINF (serial input forward) port instead of the parallel DATA input.
- Initialize SINF and ND to 0. - Assert GSR for one or two clock cycles. - Release for one cycle. - Assert ND High on the falling edge of the clock for one cycle and release. - Assert SINF High on the falling edge of the clock at the same time ND is de-asserted. Assert for one cycle and release.
One cycle after RFD goes High, repeat:
- Assert ND High on the falling edge of the clock for one cycle and release. - Assert SINF High on the falling edge of the clock at the same time ND is de-asserted. Assert for one cycle and release.
Repeat the "subsequence" of steps (each time RFD goes high) for as many cycles as needed, and observe the output at the RSLT port. The RSLT output is valid when RDY is high, for the full duration of its assertion.
NOTE: For a single-cascade mode filter, a one-clock cycle delay occurs between the assertion of ND and SINF to compensate for the absence of a parallel-to-serial converter at the front of the filter when cascade mode is selected. The timing diagram (Figure 3) in the SDA FIR data sheet does not apply to this situation.
Figure 1 illustrates a sample simulation session using the Foundation gate-level simulator:
Figure 1- Simulation of Single Cascade Mode SDA FIR Filter