AR# 46760

Description

The following answer record has some suggestions that can be used to help debug implementation issues relating to fabric

NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.

Solution

Below are some suggestions that might help to resolve implementation related issues relating to fabric resources:

• Its always a good idea to look at the current list of known issues in software for the 7 Series devices. Please refer to (Xilinx Answer 40905).
• If you are seeing an implementation error/warning that you cannot explain, it is generally a good idea to go through each of the different report files and see if there are any clues that will explain why you are seeing this issue. In particular, look for warning messages that may help show where in your design the root of the issue is at.
• Always check the appropriate users guide and verify that you are using fabric resources legally. (http://www.xilinx.com/support/documentation/7_series.htm)
• FPGA Editor and PlanAhead are each powerful tools that can be used to help understand any routing/placement issues. Use these tools to look at your particular placement/routing in the design. Sometimes this can give you insight as to why you are seeing the error/warning message
  • In extreme cases, you can hand place or route parts of the design which may work around certain issues (for power users only)

If you still can't resolve any implementation related fabric issues, please open up a case with Xilinx Technical Support (http://www.xilinx.com/support/clearexpress/websupport.htm)

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