AR# 46764


Spartan-6 FPGA Solution Center - Design Assistant


TheSpartan-6 FPGA Design Assistant walks you through the recommended design flow forSpartan-6 FPGA while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently withSpartan-6 FPGA.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


First, select the design phase where you have a question or are troubleshooting an issue related to yourSpartan-6 FPGA design.This ensures theDesign Assistant points you to the information you need to move forward with your design.

(Xilinx Answer 46795) Getting Started with theSpartan-6 FPGA
(Xilinx Answer 46739) Designing fortheSpartan-6 FPGA
(Xilinx Answer 46794) Board Level Considerations
(Xilinx Answer 46789) Troubleshooting - Clocking, Fabric, block RAM/FIFO

* For troubleshooting other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44744 Spartan-6 FPGA Solution Center N/A N/A

Associated Answer Records

AR# 46764
Date 12/15/2012
Status Active
Type General Article
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