AR# 46765


Spartan-6 FPGA Design Assistant - Using SRLs to conserve resources


This Answer Record discusses how shift register look-up tables (SRLs) can be used to help conserve resources in fabric.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


Shift Registers in Spartan-6 FPGA are most optimized for implementation in the SLICEMs. A SLICEM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can delay serial data anywhere from one to 32 clock cycles. The shiftinD and shiftoutQ lines cascade LUTs to form larger shift registers. The four LUTs in a SLICEM can thus be cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift registers across more than one SLICEM.

Applications requiring delay or latency compensation use these shift registers to develop efficient designs. Shift registers are also useful in synchronous FIFO and content addressable memory (CAM) designs.

Resets should not be used on shift registers in your design, as this requires additional logic around the SLICEM SRLwhich can reduce performance and increases the amount of logic needed to implement the shift register.

For more information on using SRLs in your design, see the section on SRLs in the HDL Coding Practices to Accelerate Design Performance White Paper (WP231):

Also reference the Spartan-6 FPGA CLB User Guide (UG384):

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44744 Spartan-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46745 Spartan-6 FPGA Design Assistant - Designing configurable logic structures in Spartan-6 FPGAs N/A N/A
AR# 46765
Date 12/15/2012
Status Active
Type General Article
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