AR# 46791

Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems

Description

This Answer Record helps guide you to solutions to common problems with the fabric resources inSpartan-6FPGAdesigns.

NOTE:This Answer Record is part of the XilinxSpartan-6FPGA Solution Center(Xilinx Answer 44744).The XilinxSpartan-6FPGASolution Center is available to address all questions related toSpartan-6devices. Whether you are starting a new design withSpartan-6FPGA or troubleshooting a problem, use theSpartan-6FPGA Solution Center to guide you to the right information.

Solution

Select from the following list of common fabric related problems. Each Answer Record helps guide you to a solution.

(Xilinx Answer 40911)Spartan-6 What is the POR (Power on Reset) Threshold Voltage?
(Xilinx Answer 23228)Spartan-3/-3E/-3A/-6 BUFGMUX - What is the setup time for the select or enable signal of BUFGMUX?
(Xilinx Answer 44174)Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup
(Xilinx Answer 39999) Design Advisory for Spartan-6 - 9K Block RAM Initialization Support
(Xilinx Answer 34533) Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap
(Xilinx Answer 34541) Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM SDP Port Width Restriction
(Xilinx Answer 38408)Design Advisory for Spartan-6 - IODELAY2; Late and Early Edge Delays and Single Data Bit Corruption
(Xilinx Answer 39046) Spartan-6 IODELAY2 - Late Data Edge and Early Data Edge Timing Analysis
(Xilinx Answer 40221) Spartan-6 - For how long should the BITSLIP in the ISERDES be asserted?
(Xilinx Answer 41083) Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon
(Xilinx Answer 42796) Spartan-6 - IODELAY2 How long does it take for BUSY to assert/de-assert?
(Xilinx Answer 41356) Design Advisory for Lower Power Spartan-6 -1L Speed Grade - IODELAY2 Support Restricted to Tap 0
(Xilinx Answer 34276) Spartan-6 FPGA - Can the IODELAY2 be used to delay an output in Variable Mode?
(Xilinx Answer 34313) Spartan-6 I/O Banking Rules - Output I/O Standard Restrictions
(Xilinx Answer 34617) Spartan-6 Phase Detector usage
(Xilinx Answer 35073) Correct attribute values are not passed on when "networking_pipelined" is selected
(Xilinx Answer 35783) Spartan-6 - How are the IODELAY2 tap delays calculated?
(Xilinx Answer 37293) Spartan-6, IODELAY2 - Do all interfaces need to be constantly calibrated? If so, how often?
(Xilinx Answer 37349) Spartan-6, IODELAY2 - What is Fmincal and how is it affected by SDR and DDR data rates?

If you still have a problem after running through the suggestions, open up a WebCase through Xilinx Technical Support:

http://www.xilinx.com/support/clearexpress/websupport.htm

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
44744	Spartan-6 FPGA Solution Center	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
46789	Spartan-6 FPGA Design Assistant - Troubleshooting	N/A	N/A
37349	Spartan-6, IODELAY2 - What is Fmincal and how is it affected by SDR and DDR data rates?	N/A	N/A
34313	Spartan-6 I/O Banking Rules - Output I/O Standard Restrictions	N/A	N/A
41356	Design Advisory for Lower Power Spartan-6 -1L Speed Grade - IODELAY2 Support Restricted to Tap 0	N/A	N/A
42796	Spartan-6 - IODELAY2 How long does it take for BUSY to assert/de-assert?	N/A	N/A
39046	Spartan-6 IODELAY2 - Late Data Edge and Early Data Edge Timing Analysis	N/A	N/A
34541	Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM Simple Dual Port (SDP) Data Width Restriction	N/A	N/A
44174	Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup	N/A	N/A
23228	Spartan-3/-3E/-3A/-6 BUFGMUX - What is the setup time for the select or enable signal of BUFGMUX?	N/A	N/A
40911	Spartan-6 What is the POR (Power on Reset) Threshold Voltage?	N/A	N/A
41083	Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon	N/A	N/A
40221	Spartan-6 - For how long should the BITSLIP in the ISERDES be asserted?	N/A	N/A
39999	Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support	N/A	N/A
38408	Design Advisory for Spartan-6 - IODELAY2; Late and Early Edge Delays and Single Data Bit Corruption	N/A	N/A
37293	Spartan-6, IODELAY2 - Do all interfaces need to be constantly calibrated? If so, how often?	N/A	N/A
35783	Spartan-6 - How are the IODELAY2 tap delays calculated?	N/A	N/A
34617	Spartan-6 Phase Detector usage	N/A	N/A
34533	Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap	N/A	N/A
34276	Spartan-6 FPGA - Can the IODELAY2 be used to delay an output in Variable Mode?	N/A	N/A

AR# 46791
Date	02/07/2013
Status	Active
Type	General Article
Devices	Spartan-6 LX Spartan-6 LXT

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