2. Support
  3. AR# 4679: A1.5/F1.5 Virtex Map reports that an output is not connected, but does not trim the logic: Warning:xvkdr - blockcheck
  4. AR# 46793: Virtex-6 Integrated Block for PCI Express v2.5 - A timing constraint for x8 gen2 (ML605) is incorrect

AR# 46793

Virtex-6 Integrated Block for PCI Express v2.5 - A timing constraint for x8 gen2 (ML605) is incorrect

Description

Version Found: v2.5
Version Resolved and other Known Issues: see (Xilinx Answer 45723)
The UCF for the ML605 has an incorrect timing constraint when the core is generated for x8 gen2

Solution


To resolve this issue, make the following modification to the UCF file:

From:
TIMESPEC "TS_CLK_500" = PERIOD "CLK_500" TS_SYSCLK*2.0 HIGH 50 % PRIORITY 1 ;

To:
TIMESPEC "TS_CLK_500" = PERIOD "CLK_500" TS_SYSCLK*5.0 HIGH 50 % PRIORITY 1 ;

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History
07/06/2012 - Initial release


AR# 46793
Date 07/06/2012
Status Active
Type ??????
IP