You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
Virtex-6 Integrated Block for PCI Express v2.5 - A timing constraint for x8 gen2 (ML605) is incorrect
Version Found: v2.5
Version Resolved and other Known Issues: see (Xilinx Answer 45723)
The UCF for the ML605 has an incorrect timing constraint when the core is generated for x8 gen2
To resolve this issue, make the following modification to the UCF file:
TIMESPEC "TS_CLK_500" = PERIOD "CLK_500" TS_SYSCLK*2.0 HIGH 50 % PRIORITY 1 ;
TIMESPEC "TS_CLK_500" = PERIOD "CLK_500" TS_SYSCLK*5.0 HIGH 50 % PRIORITY 1 ;
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
07/06/2012 - Initial release
Was this Answer Record helpful?
- Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )