UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 4686: 4.1i UniSim - Using the VHDL ROC (Reset On Configuration) Component

AR# 4686

4.1i UniSim - Using the VHDL ROC (Reset On Configuration) Component

Description


General Description:

In the M1.4 release, a component called ROC (Reset On Configuration) was introduced to VHDL simulation. This component allows functional and timing simulation of the behavior for globally resetting the device upon power-up when an external global reset pin is not present. The ROC will apply a one-shot reset pulse from time 0 of the simulation to a specified time later in the simulation, which simulates the power-up reset sequence of configuration of the FPGA/CPLD.



This Answer Record describes how to use the ROC with a VHDL simulation, although it will not refer to any specific simulators.



NOTE: The ROC component will be removed by the Xilinx tools when the synthesized design is run through implementation.

Solution


To use the ROC in your VHDL code, the component needs to be instantiated into the design and connected to the asynchronous preset or reset of every inferred or instantiated register or latch in the design.



Instantiate the ROC according to the following example:



architecture XILINX of roc_example is



signal GLOBAL_RESET: STD_LOGIC;

component ROC port (O: out STD_LOGIC);



begin



RESET_ON_CONFIG: roc port map (O=>GLOBAL_RESET);



end XILINX;





In the above instantiation example, the GLOBAL_RESET signal should be connected to all inferred and instantiated registers with an active high polarity. For example, a counter may be coded as follows:



COUNT4: process (GLOBAL_RESET, CLOCK, LOAD, CE)

begin

if (GLOBAL_RESET = '1') then

QOUT <= "0000";

elsif (CE = '1') then

if (CLOCK'event and CLOCK = '1') then

if (LOAD = '1') then

QOUT <=DATA;

else QOUT <= QOUT + 1;

end if;

end if;

end if;

end process COUNT4;





The value or PERIOD of time that the one-shot pulse is applied can be specified by the user from a VHDL configuration statement in the design's testbench. If you are using Xilinx software that is version 1.5 or later, the default PERIOD for the ROC is 100ns. If you are using the 1.4 patched version of NGD2VHDL from the Xilinx FTP site, the PERIOD must be specified from the command line by using the -rpw switch. (The 1.4 version of NGD2VHDL does not have a default value and must have a configuration to initialize the ROC component.)



In order to specify/override an ROC value, the following configuration may be added to the testbench file for the design:



---------------------------------------------------------------------

Use this configuration for RTL simulation

---------------------------------------------------------------------



CONFIGURATION RTL_simulation OF <testbench_entity_name> IS

FOR <testbench_architecture_name>

FOR <design_instance_name>:<design_entity_name>

FOR <design_architecture_name>

FOR <ROC_instance_name>:ROC USE ENTITY UNISIM.ROC(ROC_V)

generic map (WIDTH => <PERIOD> ns);

END FOR;

END FOR;

END FOR;

END FOR;

END RTL_simulation;



-----------------------------------------------------------------------------

Use this configuration for Post M1 simulation

-----------------------------------------------------------------------------



--CONFIGURATION Post_M1_simulation OF <testbench_entity_name> IS

-- FOR <testbench_architecture_name>

-- FOR <design_instance_name>:<design_entity_name>

-- FOR STRUCTURE

-- FOR ROC_NGD2VHDL:ROC USE ENTITY WORK.ROC(ROC_V)

-- generic map (WIDTH => <PERIOD> ns);

-- END FOR;

-- END FOR;

-- END FOR;

-- END FOR;

--END Post_M1_simulation;



All items above within <> should be filed in with names from the testbench/design and the desired values for the PERIOD.





An example testbench and VHDL design file is included in Resolutions 2 and 3.



--------------------------------------------------------------------------------

TESTBENCH_ROC.VHD

- Testbench file for testing ROC_EXAMPLE.VHD

- Example code using the ROC buffer

--------------------------------------------------------------------------------



LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE std.textio.ALL;



ENTITY testbench IS

END testbench;



ARCHITECTURE tutorial OF testbench IS





-- Component Declaration of the Top-Level of Design



COMPONENT roc_example

PORT ( LOAD : in STD_LOGIC;

CLOCK : in STD_LOGIC;

CE : in STD_LOGIC;

DATA : in STD_LOGIC_VECTOR (3 downto 0);

COUT : out STD_LOGIC_VECTOR (3 downto 0));

END COMPONENT;





-- Signals Used to Connect the Design's Ports to Testbench



SIGNAL load_signal: STD_LOGIC;

SIGNAL clock_signal: STD_LOGIC;

SIGNAL ce_signal: STD_LOGIC;

SIGNAL data_signal: STD_LOGIC_VECTOR (3 downto 0);

SIGNAL cout_signal: STD_LOGIC_VECTOR (3 downto 0);



BEGIN



-- Instantiatation of the Design



uut : roc_example PORT MAP (LOAD => load_signal,

CLOCK => clock_signal,

CE => ce_signal,

DATA => data_signal,

COUT => cout_signal);





-- Start the Simulation



stimulus : PROCESS



BEGIN





-- Initialize All Input Ports



load_signal <= '0';

clock_signal <= '0';

ce_signal <= '0';

data_signal <= "0000";





-- Wait until Global Reset is Finished



WAIT FOR 200 ns;





-- Apply Design Stimulus



ce_signal <= '1';



LOOP

WAIT FOR 25 ns;

clock_signal <= not (clock_signal);

END LOOP;





-- Process Finished!



END PROCESS stimulus;



END tutorial;





-- Use this configuration for RTL simulation



CONFIGURATION RTL_simulation OF testbench IS

FOR tutorial

FOR uut:roc_example

FOR xilinx

FOR RESET_ON_CONFIG:ROC USE ENTITY UNISIM.ROC(ROC_V)

generic map (WIDTH => 200 ns);

END FOR;

END FOR;

END FOR;

END FOR;

END RTL_simulation;





-- Use this configuration for Post-M1 simulation



--CONFIGURATION Post_M1_simulation OF testbench IS

-- FOR tutorial

-- FOR uut:roc_example

-- FOR STRUCTURE

-- FOR ROC_NGD2VHDL:ROC USE ENTITY WORK.ROC(ROC_V)

-- generic map (WIDTH => 200 ns);

-- END FOR;

-- END FOR;

-- END FOR;

-- END FOR;

--END Post_M1_simulation;



----------------------------------------------------------------------------------------------

-- ROC_EXAMPLE.VHD Version 1.1

-- Example code using the ROC model to reset 4-bit counter

-----------------------------------------------------------------------------------------------



-- pragma translate_off



Library UNISIM;

use UNISIM.Vcomponents.all;



-- pragma translate_on



LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_unsigned.all;



entity roc_example is

port (LOAD, CLOCK: in STD_LOGIC;

CE: in STD_LOGIC;

DATA: in STD_LOGIC_VECTOR (3 downto 0);

COUT: out STD_LOGIC_VECTOR (3 downto 0));

end roc_example;



architecture XILINX of roc_example is



signal QOUT: STD_LOGIC_VECTOR (3 downto 0);

signal GLOBAL_RESET: STD_ULOGIC;



COMPONENT roc port (O: out STD_LOGIC);

END COMPONENT;



begin





-- Reset On Configuration (ROC) Buffer Instantiation



RESET_ON_CONFIG: roc port map (O=>GLOBAL_RESET);





-- Behavioral description of a 4-bit Loadable Counter with Asynchronous Reset and Clock Enable



COUNT4: process (GLOBAL_RESET, CLOCK, LOAD, CE)

begin

if (GLOBAL_RESET = '1') then

QOUT <= "0000";

elsif (CE = '1') then

if (CLOCK'event and CLOCK = '1') then

if (LOAD = '1') then

QOUT <=DATA;

else QOUT <= QOUT + 1;

end if;

end if;

end if;

end process COUNT4;



COUT <= QOUT;



end XILINX;
AR# 4686
Date 11/23/2011
Status Archive
Type General Article

By using this website, I accept the use of cookies.   Learn more

Page Bookmarked