AR# 4686: 4.1i UniSim - Using the VHDL ROC (Reset On Configuration) Component
4.1i UniSim - Using the VHDL ROC (Reset On Configuration) Component
In the M1.4 release, a component called ROC (Reset On Configuration) was introduced to VHDL simulation. This component allows functional and timing simulation of the behavior for globally resetting the device upon power-up when an external global reset pin is not present. The ROC will apply a one-shot reset pulse from time 0 of the simulation to a specified time later in the simulation, which simulates the power-up reset sequence of configuration of the FPGA/CPLD.
This Answer Record describes how to use the ROC with a VHDL simulation, although it will not refer to any specific simulators.
NOTE: The ROC component will be removed by the Xilinx tools when the synthesized design is run through implementation.
To use the ROC in your VHDL code, the component needs to be instantiated into the design and connected to the asynchronous preset or reset of every inferred or instantiated register or latch in the design.
Instantiate the ROC according to the following example:
architecture XILINX of roc_example is
signal GLOBAL_RESET: STD_LOGIC;
component ROC port (O: out STD_LOGIC);
RESET_ON_CONFIG: roc port map (O=>GLOBAL_RESET);
In the above instantiation example, the GLOBAL_RESET signal should be connected to all inferred and instantiated registers with an active high polarity. For example, a counter may be coded as follows:
COUNT4: process (GLOBAL_RESET, CLOCK, LOAD, CE)
if (GLOBAL_RESET = '1') then
QOUT <= "0000";
elsif (CE = '1') then
if (CLOCK'event and CLOCK = '1') then
if (LOAD = '1') then
else QOUT <= QOUT + 1;
end process COUNT4;
The value or PERIOD of time that the one-shot pulse is applied can be specified by the user from a VHDL configuration statement in the design's testbench. If you are using Xilinx software that is version 1.5 or later, the default PERIOD for the ROC is 100ns. If you are using the 1.4 patched version of NGD2VHDL from the Xilinx FTP site, the PERIOD must be specified from the command line by using the -rpw switch. (The 1.4 version of NGD2VHDL does not have a default value and must have a configuration to initialize the ROC component.)
In order to specify/override an ROC value, the following configuration may be added to the testbench file for the design: