AR# 46880


Zynq-7000 Example Design - Linear QSPI Performance (Max Effective Throughput)


This example design shows how to achieve QSPI (in Linear Mode) Maximum Effective Throughput with a 100 MHz SPI clock.


Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. 

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.

Limited support is provided by Xilinx on these Example Designs.

Implementation Details
Design TypePS only
SW TypeStandalone
CPUsSingle CPU @ 720MHz
PS Features

QSPI ( in linear mode) with SPI clock @ 100MHz
DDR @ 533MHz

PL Cores--
Boards/ToolsZC702 (modified to have MIO[8] n.c. in order to enable the qspi loopback).
Xilinx Tools VersionEDK 14.1
Other details--
Files Provided
 Snippet of code.

 Block Diagram




In order to achieve Linear Mode Maximum Effective Throughput with 100 MHz SPI clock, the DMA controller has been used.

This very flexible DMA can execute a few lines of microcode in order to transfer data from the Linear QSPI to DDR.

Below is an example of microcode that moves 256 Kbytes from LQSPI to DDR:

DMAMOV SAR, 0xFC000000
DMAMOV DAR, 0x00300000

The QSPI is set to operate in Linear Mode: single SPI flash memory, Fast read quad I/O (LQSPI_CFG = 0x82FF04EB ).

SPI reference clock: 200 MHz

SPI clock: 100 MHz (with DIV2)

The CPU is running at 720 MHz and DDR at 533 MHz.

Transfer time is calculated by counting elapsed counter ticks in the CP15 performance monitor register.

Step-by-step Instructions

  1. Open Xilinx SDK.
  2. Create a Zynq Empty Application Project.
  3. Import the attached xdmaps_example_no_intr.c (modified from the example provided by the tools to accommodate LQSPI):
  4. Be sure that SRC_LQSPI is defined and PROCESSOR_TICKS_TO_US matches your system settings.


Note: I also attached an example tested on 14.2. 

It does not include the "transfer time" calculation, but it shows how to use the DMA to read data from the qspi.

Expected results

Following are the results for 1.0 silicon:

Read mode at 100 MHZ (DIV2)

Average PL330 transfer time to DDR


% Bandwidth Vs. theoretical

50 MBytes/sec
QUAD OUTPUT - FAST READ (0x6B) ~ 31~ 62%
QUAD IO - FAST READ (0xEB)~ 36~ 72%


Associated Attachments

Name File Size File Type
xdmaps_example_w_intr_14_2.c 12 KB C 7 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51779 Zynq-7000 SoC - Example Designs and Tech Tips N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
50991 Zynq-7000 SoC - What devices are supported for configuration? N/A N/A
AR# 46880
Date 05/18/2018
Status Active
Type General Article
Boards & Kits
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