UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 46881: Zynq-7000 Debug - How do I set up a third-party debug environment on the ZC702 board?

AR# 46881

Zynq-7000 Debug - How do I set up a third-party debug environment on the ZC702 board?

Description

How do I set up a third-party debug environment for Zynq-7000 platform on the ZC702 board?

Solution

Zynq platform supports two different JTAG modes:

  • Cascaded JTAG Chain Mode
  • Independent JTAG Chain Mode

The mode is determined through Mode Input at the time the system comes out of reset.

For more information, refer to chapter 27 of the Zynq-7000 EPP Technical Reference Manual (UG585).

ZC702 BOARD :CASCADED JTAG CHAIN MODE

  1. Configure the following jumper and switch settings:

 

boot_mode[3]

boot_mode[2]

boot_mode[1]

boot_mode[0]

 

ZC702 (Rev 1.0)SW16-4SW16-3SW16-2SW16-1SW10

Cascade JTAG

 

 

 

0

 

JTAG Mode

0

0

0

 

 

PJTAG Connector ( J58 )

 

 

 

 

11

 

  1. Connect the third-party debug cable to the PJTAG Connector (J58).
  2. Power on the board.
  3. Open and Run the third-party debug software:
    1. For ARM DS-5, see (Xilinx Answer 47764).
    2. For Lauterbach, see (Xilinx Answer 47767).

ZC702 BOARD :INDEPENDENT JTAG CHAIN MODE

  1. Program the QSPI device with a valid image of FSBL and u-boot.
  2. Configure the following jumper and switch settings:

 

boot_mode[3]

boot_mode[2]

boot_mode[1]

boot_mode[0]

 

ZC702 (Rev 1.0)SW16-4SW16-3SW16-2SW16-1SW10

Independent JTAG

 

 

 

1

 

Quad SPI Mode

1

0

0

 

 

Platform USB Connector ( J2 )

 

 

 

 

10

 

  1. Connect the third-party debug cable to the PL PJTAG Connector (J41).
  2. Connect the Platform USB cable to the Platform USB Connector (J2).
  3. Power on the board.
  4. Stop the execution of uboot.
  5. Program the bitstream that routes the JTAG signals out from PL (using impact).
  6. Open and Run the third-party debug software:
    1. For ARM DS-5, see (Xilinx Answer 47764).
    2. For Lauterbach, see (Xilinx Answer 47767).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
50863 Zynq-7000 SoC - Debug N/A N/A
52540 Zynq-7000 SoC - Frequently Asked Questions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
47767 Zynq-7000 Debug - Lauterbach Startup Script for ZC702 N/A N/A
47764 Zynq-7000 Debug - ARM DS-5 Getting Connected Guide on ZC702 N/A N/A
52184 Zynq-7000 SoC ZC702 Evaluation Kit - How does SW16 correlate to jumpers J20,​ J21,​ J22,​ J25 and J26? N/A N/A
AR# 46881
Date 05/18/2018
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.1
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
Page Bookmarked