Can the MIG core use the input or output clocks from the Zynq processing system (PS)?
No, MIG cannot use the input clock to the PS or the outputs of the Phase Locked Loops (PLLs) from the Zynq PS.
The input clock is a dedicated route that only connects to the PS.
The output clocks from PLLs, therefore they will not meet the jitter requirements that are necessary to run the MIG clock structure.
The MIG clocking structure requires that the input clock come from a clock capable I/O in order to drive the clocking backbone.
The clocking backbone is not accessible via BUFG/BUFR/BUFH and therefore using a clock from another PLL is not an option.
See (Xilinx Answer 40603) for more information about 7 Series MIG clocking.
Revision History
09/19/2014 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40603 | MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines | N/A | N/A |
| AR# 46906 | |
|---|---|
| Date | 09/22/2014 |
| Status | Active |
| Type | General Article |
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