(VC707) PCIe Design Creation (vc707_PCIe_pdf_xtp144_13.4.pdf) page 21 states:
However, modifying the design to add this extra constraint to the UCF file results in a MAP error during compilation of the design:
How can I resolve this and compile the design error-free?
This LOC to pin AP24 is a legacy constraint from a previous architecture.
For the VC707, the "emcclk" pin is AP37, not AP24.
The LOC constraint in the UCF file should read:
The VC707 PCIe Design Creation PDF has been updated to reflect this correct constraint.
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