What is the endianness of gateway in/out blocks in Sysgen?
For example, if I have a 32-bit wide gateway out, the generated code is a standard_logic_vector(31 downto 0).
So which is the most significant bit of the actual data?
It is important to draw a distinction between endianness and bit indexing.
Endianness refers to the byte addressing of a particular word.
You probably do not need to know the endianness of the data (in the strict sense of the word), as this is somewhat arbitrary without proper context.
Instead it is useful to know which bit index corresponds to the MSB of the actual data and how the HDL corresponds to Sysgen.
The answer to that question is that Sysgen generates code as standard_logic_vector(MSB downto LSB).
The most significant bit in this case is bit 31.