MIG Virtex-6 DDR2/DDR3 - x4 RDIMMs have incorrect mapping
Description
MIG generates a linear address scheme for the dq-dqs mapping of x4 RDIMM's, whereas this is non-linear on the memory part.
Solution
This discrepancy was discovered in MIG v3.9 resulting in incorrect x4 RDIMM pin allocation.
Starting with MIG v3.91, a notice was added to the MIG GUI to inform user that MIG does not allocate pins for x4 RDIMM as per the memory part datasheet when x4 RDIMM is selected.
There are currently no plans to fix this. Only x4 RDIMM's are affected.
To work around this issue, manually modify the RTL to properly target the module.