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AR# 47031

13.4 EDK - The computed value for the VCO operating frequency of PLL_ADV instance falls above the operating range


After I modify the clock generator parameters, MAP shows errors similar to the following:

ERROR:PhysDesignRules:2449 - The computed value for the VCO operating frequency
   of PLL_ADV instance
   clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst is
   calculated to be 3000.000000 MHz. This falls above the operating range of the
   PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please
   adjust either the input frequency CLKINx_PERIOD, multiplication factor
   CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to achieve a VCO
   frequency within the rated operating range for this device. 
ERROR:Pack:1642 - Errors in physical DRC.


When changing the clock generator parameters, please also change these settings:

1. The clock input ports period in MHS
2. The clock inputs period constraint in the UCF file.
AR# 47031
Date 03/05/2015
Status Active
Type General Article
  • EDK - 13.4