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AR# 47043

Design Advisory MIG 7 Series - Addition of MMCM to Clocking Structure Starting with v1.5 (available with ISE Design Suite 14.1)

Description

Starting with the release of MIG 7 series v1.5, available with ISE 14.1 design tools, an MMCM has been added to the pre-existing clocking structure. Prior to v1.5, a single PLL was used to create PLL clock outputs that route:

  • on the 7 series frequency backbone (mem_refclk, sync_pulse and freq_refclk)
  • on a global clock network through a BUFG (phy_clk)

The PHY requires that these clocks be aligned. However, characterization work has shown that the change in BUFG insertion delay over voltage and temperature might cause the BUFG clock to become unaligned in phase to the frequency backbone clocks. This misalignment causes the PHY Control Block to become out of sync.

NOTE: The PLL and MMCM are required for all memory standards at all frequencies and must be located in the same bank as the Address/Control byte groups. All users must move to MIG v1.5 to ensure the PHY Control Block stays in sync.

Solution

To remove the BUFG insertion delay and keep all MIG clocks phase aligned over voltage and temperature, the BUFG "phy_clk" must be deskewed using an MMCM. The following figure displays the clocking structure used by 7 series MIG starting with v1.5.

mig_clock_struc.JPG
mig_clock_struc.JPG



Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A
AR# 47043
Date Created 04/12/2012
Last Updated 03/06/2013
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series