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AR# 47073

13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis

Description

Starting from ISE 13.3, XST new parser will give the following errorfor cases where there are multiple signal edgesin the sensitive list and not all of the signals are used in the process/always block See (Xilinx Answer 44499).


"ERROR:HDLCompiler:1128 - "multiple_clocks_1128.v" Line 16: Assignment under multiple single edges is not supported for synthesis."


An example code which can cause this error is as follows,

always @(posedge clk or posedge reset) begin

/*
if (reset)
out <= 1'b0;
else
*/
out <= d;
end

However, XST gives this errorfor the following code incorrectlyin spite of rst signal being actually used in the always block. How to resolve this issue?

integer i;

always @ (posedge clk or posedge rst)
begin
for (i=0 ; i<16 ; i=i+1)
begin
if(rst)
out[i] <= 1'b0;
else
out[i] <= in[i];
end
end

Solution

The following are couple of workarounds that can be used toget aroundthis issue:

Workaround:1

The severity of the error message can be changed to warning and synthesis continued as follows:

-change_error_to_warning "HDLCompiler:1128"

Workaround:2

Put the for loop outside the always block and use generate statement.

genvar i;

generate
for (i=0 ; i<16 ; i=i+1)
begin
always @ (posedge clk or posedge rst)
begin
if(rst)
out[i] <= 1'b0;
else
out[i] <= in[i];
end
end
endgenerate

AR# 47073
Date Created 05/01/2012
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 13.4