Description

If I generate a v3.167 32-bit Initiator/Target for PCI core, the following error occurs:

"ERROR:coreutil - ERROR: Failed to output eJava for com.xilinx.ip.pci32_v3_167.CopyFilesetZipPCI
null
java.lang.NullPointerException
at com.xilinx.ip.pci32_v3_167.CopyFilesetZipPCI.doCopy(Unknown Source)
at com.xilinx.ip.pci32_v3_167.CopyFilesetZipPCI.writeFile(Unknown Source)
at com.xilinx.iputils.ejava.EJavaUtilities.doOutput(Unknown Source)
at com.xilinx.iputils.ejava.EJavaUtilities.execute(Unknown Source)
at com.xilinx.sim.base.Sim.generateAssociatedFiles(Unknown Source)
at com.xilinx.sim.base.Sim.generateAssociatedFiles(Unknown Source)
at com.xilinx.sim.base.HDLSim.deliverAssociatedFiles(Unknown Source)
at com.xilinx.sim.base.HDLSim.implement(Unknown Source)
at com.xilinx.sim.base.HDLSim.buildStructure(Unknown Source)
at com.xilinx.sim.netlisters.GenerationUtilities.buildHDLSim(Unknown Source)
at com.xilinx.sim.netlisters.GenerationAPI.getImplementedSim(Unknown Source)
at com.xilinx.sim.netlisters.GenerationAPI.generateSimCore(Unknown Source)
at com.xilinx.sim.netlisters.GenerationAPI.generate(Unknown Source)
at com.xilinx.sim.netlisters.GenerationAPI$1.construct(Unknown Source)
at com.xilinx.coreutil.util.guis.SwingWorker$2.run(Unknown Source)
at java.lang.Thread.run(Unknown Source)
WARNING:sim:93 - NGC output will not be generated for this core.
WARNING:sim:95 - Structural Verilog netlist output will not be generated for this core.
Finished Generation.
Generating IP instantiation template..."

Solution

This issue has been resolved in ISE Design Suite 14.3.

The problem was due to the build process for this core adding absolute paths instead of relative paths in the archive file (C:\xilinx\14.2\ISE_DS\ISE\coregen\ip\xilinx\network\com\xilinx\ip\pci64_v3_167\fileset\v3.1.166.zip). All of the paths in the archive should begin with the v3.1.166 directory.

To work around this issue, perform one of the following

• Use ISE Design Suite 14.3 or later.
• Use an earlier version of the ISE design tools (such as 13.1) to generate the core. There is no difference in the core generated in ISE Design Suite version 13.1 and what would be generated in 14.3.
• Copy the v3.1.166.zip file from the ISE Design Suite 13.1 install area to the install area of the ISE Design Suite version being used.
• Edit the paths in the v3.1.166.zip and remove all directory references before the v3.1.166 directory.

Revision History

01/16/2013 - Updated to include 14.3
04/05/2012 - Initial release

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