AR# 47108: MIG 7 Series DDR2/DDR3 - Synplify Pro fails when "I/O Power Reduction" is enabled
AR# 47108
MIG 7 Series DDR2/DDR3 - Synplify Pro fails when "I/O Power Reduction" is enabled
Description
Version Found: v1.5 Version Resolved and other Known Issues: See(Xilinx Answer 45195).
MIG 7 Series DDR2/DDR3 designs with the "I/O Power Reduction" GUI option enabled, placed in HR banks, and using Synplify Pro F-2012.03 will fail in NGDBuild with the following error:
ERROR:NgdBuild:947 - bidirect pad net 'ddr3_dq_c[0]' is driving non-input buffer(s): pin I on block ddr3_dq_obuf[0] with type OBUF
Solution
These failures are due to new I/O primitives MIG uses when HR banks are selected in the GUI with I/O Power Reduction enabled.
In these cases, IOBUF_INTERMDISABEL and IOBUFDS_INTERMDISABLE primitives are used, but Synplify is incorrectly inserting an OBUF between these primitives and the pad.
Workaround:
There is no issue with the XST synthesis flow, but if Synplify Pro is required you can generate the design with I/O Power Reduction disabled.
This design uses the IOBUF and IOBUFDS primitives which cause no issues with Synplify.
If the I/O Power Reduction option is enabled, you can work around the problem by modifying the RTL parameters in top level files.
The DATA_IO_IDLE_PWRDWN and DATA_IO_PRIM_TYPE parameters need to be changed to "OFF" and "DEFAULT" from "ON" and "HR_LP" respectively.
With these changes to the RTL parameters, IOBUF and IOBUFDS primitives will be used for memory I/Os instead of IOBUF_INTERMDISABLE and IOBUFDS_INTERMDISABLE respectively.
This issue only exists for DDR2/DDR3 designs and Synplify plan to fix this in a future release.