AR# 47128

Description

Solution

1. GTH Transceiver Attribute Updates for Initial Engineering Sample (ES) Silicon

This table shows the GTH attribute updates required for reliable operation of the Initial ES silicon as noted under "ISE 14.1."

The following attribute updates marked as "ISE 14.1" can be generated natively when using v2.2 of the 7 series FPGA Transceiver Wizard in the ISE 14.2/Vivado 2012.2 or later tools.

GTH Attributes

Notes:

Notes:
1. Programmable, set to 800 mV.
2. Must be set manually through version ISE version 14.4
3. For simulation speed-up, CFOK_CFG needs to be set a different value. Please see (Xilinx Answer 47318) for details.
4. The RXCDR_CFG settings are preliminary and are under characterization. The final settings will be added when available.
5. The RXCDRLOCK port is not supported. The port RXCDRLOCK is only a coarse indicator of CDR lock and it is recommended to verify the incoming data as well.

GTH Ports

Notes:
1. In DFE mode, the RXDFEAGCHOLD and RXDFELFHOLD should be asserted after training (waiting time of "T_DLOCK" = 1.0207E+08 bits in DFE mode) to freeze the AGC adapt value.
2. In LPM mode, the RXLPMHFHOLD and RXLPMLFHOLD should be asserted after training (waiting time of "T_DLOCK" to be determined for LPM mode, but the same value above in DFE mode can be used) to freeze the LPM adapt value.
3.RXDFEXYDEN must be set manually to 1'b1 in v2.1 or earlier of the wizardin ISE 14.1/Vivado 2012.1; set to 1'b1 by default in v2.2 or later of wizard in ISE 14.2/Vivado 2012.2 or later.

2. Use Modes

2.1. GTH Transceiver Eye Scan:
RX_DATA_WIDTH of 20 and 40 are not supported by Eye Scan. For RX_DATA_WIDTHof 16, 32, or 64, the use mode described in (Xilinx Answer 47425) must be followed to enable proper operation of Eye Scan.

2.2. GTHE2_COMMON/BIAS_CFG Use Model Change:

BIAS_CFG is an attribute of the GTHE2_COMMON module and its value depends on the PLL driving the channel, and the correct QPLL settings are covered in the attribute table. However, for the correct BIAS_CFG to propagate through, the following use mode must be followed. Otherwise, BIAS_CFG will be set incorrectly in the software model to 64'h0000000000000000.

To use the correct BIAS_CFG value when using 7 series GTH Transceiver Wizard v2.1 or earlier, perform the following steps:

1. Instantiate GTH2_COMMON in every Quad used in the design even if the QPLL is not used in that Quad.
2. Define the correct value of BIAS_CFGin the wrapper or UCF.

Note: After setting BIAS_CFG as above, the minimum connections required so that the tools do not optimize the GTHE2_COMMON block away are as follows:

1. GTHE2_COMMON port GTREFCLK0 should be connected to the incoming reference clock.
2. GTHE2_COMMON port QPLLOUTCLK should be connected to GTHE2_CHANNEL port QPLLCLK (all the used channels on the quad).
3. GTHE2_COMMON port QPLLREFCLKSEL should be 3'b001.

The GTHE2_COMMONinstantiations should be done in the gtwizard_v2_1.v file for Verilog or gtwizard_v2_1.vhd for VHDL (gtwizard_v2_1 is the default name that will be replaced with the name that the user gives to the design onpage 1 of the wizard). The GTHE2_COMMON instantiation can be obtained from a wizard example design that uses QPLL (sample"gt_wizard_v2_2.v" and "gt_wizard_v2_2.vhd" files are attached to show an example where two GTHE2_COMMON's are instantiated).

The GTHE2_COMMON module is automatically instantiated when using the 7-Series GTH Transceiver Wizard v2.2 or later in ISE 14.2/Vivado 2012.2 or later.

2.3. Termination Use Modes:

For the different RX termination use modes, refer to (Xilinx Answer 50146).

2.4. ACJTAG Use Mode:

For details on the ACJTAG use mode, refer to (Xilinx Answer 52431).

3. Issues

3.1. Incorrect GTH Resistor Calibration:

The GTH resistor calibration circuitry on the Initial ES silicon devices may not calibrate to the expected value. For additional information, please refer to (Xilinx Answer 50147).

NOTE: After further investigation and analysis, it has been determined that there are no issues with the GTH resistor calibration circuitry . This work-around in (Xilinx Answer 50147) is not required to be implemented and should be removed. This issue will be removed from this section in afuture update to this design advisory.

4. GTH Initial ES Silicon Errata Items

4.1. GTH Transceiver Link Margin Reduction:

There can be a reduction in link margin, in the form of increased transmitter output jitter and reduced receiver input jitter tolerance, when multiple GTH channels are used. For additional information, please refer to (Xilinx Answer 50063).

4.2. RXOUTCLK Port:

The GTH transceiver RXOUTCLK port, when configured to use the RXOUTCLKPCS or the RXOUTCLKPMA path, can exhibit a phase jump of up to two UI of the line rate. This issue applies when the GTH line rate is above 8.5 Gb/s. For additional information, please refer to (Xilinx Answer 50064).

Revision History
02/08/2013 - AddedPCS_RSVD_ATTR[8] and note
01/23/2013 - Added QPLL_CLKOUT_CFG and update CPLL_CFG for PCIe Gen 1 & Gen 2
01/14/2013 - Updated the values for Bias_cfgandqpll_cfg.
10/16/2012 - Added the ACJTAG use mode.
08/09/2012 - Updated the GTHE2_COMMON/BIAS_CFG section to specify which file to update with the new instantiations and also addedan example. Also added some references to ISE 14.2/Vivado 2012.2 in general.
07/27/2012 - Updated the Incorrect GTH Resistor Calibration section that there is no issue and no work-around is required.
07/12/2012 - Updated the QPLL_CFG and QPLL_LOCK_CFG values for different line rates and updated the answer record for GTH Transceiver Link Margin Reduction.
06/28/2012 - Updated PMA_RSV2, RX_BIAS_CFG, RXDFEXYDEN values in the attributes and ports section.
05/24/2012 - Added GTHE2_COMMON use mode change, termination use modes, the Initial ES errata items section, and modified the resistor calibration section.
05/14/2012 - Added the incorrect resistor calibration section and the updated BIAS_CFG value to the table.
05/02/2012 - Initial release

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