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AR# 47190

LogiCORE IP Serial RapidIO Gen2 v1.4 - Release Notes and Known Issues for ISE 14.1 and Vivado 2012.1 Design Suites

Description

This Release Note and Known Issues Answer Record is for the LogiCORE IP Serial RapidIO Gen2 v1.4 which was released in the ISE 14.1 and Vivado 2012.1 design tools and contains the following information:
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues
  • Other Information
For installation instructions, general CORE Generator tool known issues, and design tool requirements, see the IP Release Notes Guide.

Solution

New Features:

ISE Design Suite

  • ISE 14.1 tools support
  • ChipScope tool support
  • Debug bus support
  • Hardware validated on Kintex-7 GES, Virtex-7 IES and Virtex-6 FPGA 6.25 Gb/s (see IP Release Notes Guide for more information)
  • Configurable additional link-requests before fatal
  • User-Defined port and Separate Messaging port in 5.0/6.25 Gb/s x4 configurations
  • Added Virtex-6 FPGA 6.25 Gb/s x4 support
  • Enhancements to the Example Design: Statistics Capture, Addressable Memory Space

Vivado Design Suite

  • 2012.1 design tools support

Supported Devices:

ISEDesign Suite

The following device families are supported by the core for this release:

  • Virtex-7 devices
    • Virtex-7
    • Virtex-7 -2G
    • Virtex-7 HT/XT
    • Virtex-7 Low Voltage (-2L)
  • Kintex-7 devices
    • Kintex-7
    • Kintex-7 Low Voltage (-2L)
  • Virtex-6 devices
    • Virtex-6
      • CXT/LXT/SXT/HX
    • Virtex-6 Lower Power (-1L)
      • LXT/SXT

Vivado Design Suite

The following device families are supported by the core for this release.

  • Virtex-7 devices
    • Virtex-7
    • Virtex-7 -2G
    • Virtex-7 HT/XT
  • Kintex-7 devices
    • Kintex-7

Resolved Issues:

ISE Design Suite

  • (Xilinx Answer 45866) - LogiCORE IP Serial RapidIO Gen2 v1.3 - Malformed packet generation in the receive PHY layer
  • (Xilinx Answer 46008) - LogiCORE IP Serial RapidIO Gen2 v1.3 - 'Common Transport Large System Support' bit in Processing Elements Features CAR not set correctly
  • (Xilinx Answer 46089) - LogiCORE IP Serial RapidIO Gen2 v1.3 - Incorrect two lane port support information in "Port n Control CSR Register" table
  • (Xilinx Answer 45976) - LogiCORE IP Serial RapidIO Gen2 v1.3 - "WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance..."
  • (Xilinx Answer 46629) - LogiCORE IP Serial RapidIO Gen2 v1.3 - Disabling the "Source Maintenance Support" option not supported
  • (Xilinx Answer 47103) -LogiCORE IP Serial RapidIO Gen2 v1.3 - Multiple errors in close proximity can prevent core from sending out an LRESP
  • (Xilinx Answer 47019) -LogiCORE IP Serial RapidIO Gen2 v1.3 -Core loses sync when receiving clock compensation in IDLE2
  • (Xilinx Answer 46904)- LogiCORE IP Serial RapidIO Gen2 v1.3 -Core sends out a PNA when receiving control symbols separated by less than 4 idle bytes
  • (Xilinx Answer 46905)- LogiCORE IP Serial RapidIO Gen2 v1.3 - treq_tvalid toggles continuously when treq_tready is de-asserted in the middle of data transfer

Vivado Design Suite

  • NA

Known Issues:

ISE Design Suite

Vivado Design Suite

  • (Xilinx Answer 47411) Malformed SRIO Synthesis Netlist when Hierarchy is set to 'rebuilt'
  • (Xilinx Answer 47744)IDLE2 Mode Not Supported
    Some configurations of the design may not meet timing.
  • Hardware validation has not been performed. This release is a design tools release only, and should only be used for implementation and
    simulation analysis.
  • ChipScope tool support has not been added under the Vivado design tools flow.
  • (Xilinx Answer 47919) - Example design simulation fails when LCSBA is enabled and assigned to a specific address
  • (Xilinx Answer 50139) - 16-bit Device ID width not supported

Other Information

The following answer records provide descriptions on additional features which are introduced in the LogiCORE IP Serial RapidIO Gen2 v1.4 core. This is not included in the current product guide. It will be added in the next release.

  • (Xilinx Answer 47191) LogiCORE IP Serial RapidIO Gen2 v1.4 - Where can I find a list of debug signals?
  • (Xilinx Answer 47387) LogiCORE IP Serial RapidIO Gen2 v1.4 - New Features: ChipScope in Example Design, Addressable Memory Space and Statistics Capture
  • (Xilinx Answer 41613) 7 Series FPGAs GTX/GTH transceivers known Issues and answer record list

Revision History
05/08/2012 - Initial Release
05/24/2012 - Added Link to (Xilinx Answer 50139)

AR# 47190
Date Created 05/07/2012
Last Updated 09/25/2012
Status Active
Type Release Notes
IP
  • Serial RapidIO