AR# 47208

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP SMPTE2022-5/6 Video over IP Receiver Core.

The following information is listed for each version of the core:

• New Features
• Bug Fixes
• Known Issues

Solution

• N/A

• Patch release for 14.x, available from (Xilinx Answer 55522).

• Virtex-7
• Virtex-7 Low Voltage (-2L)
• Kintex-7
• Kintex-7 Low Voltage (-2L)
• Virtex-6 CXT/LXT/SXT/HXT
• Virtex-6 Lower Power (-1L) LXT/SXT

• Fixed interoperability and improved performance to comply with latest SMPTE 2022-5/6 specification
• Tested on 14.4 and 14.5

• N/A

• N/A

• Initial Release in ISE Design Suite 14.4, Vivado 2012.24

• Virtex-7
• Virtex-7 Low Voltage (-2L)
• Kintex-7
• Kintex-7 Low Voltage (-2L)
• Virtex-6 CXT/LXT/SXT/HXT
• Virtex-6 Lower Power (-1L) LXT/SXT

• Virtex-7
• Virtex-7 Low Voltage (-2L)
• Kintex-7
• Kintex-7 Low Voltage (-2L)

• Supports SMPTE2022-5/6 released version. v2.0 and v1.0 support SMPTE2022-5/6 draft version

• N/A

• N/A

• N/A

• Initial Release in ISE Design Suite 14.2, Vivado 2012.2

• Virtex-7
• Virtex-7 Low Voltage (-2L)
• Kintex-7
• Kintex-7 Low Voltage (-2L)
• Virtex-6 CXT/LXT/SXT/HXT
• Virtex-6 Lower Power (-1L) LXT/SXT

• Virtex-7
• Virtex-7 Low Voltage (-2L)
• Kintex-7
• Kintex-7 Low Voltage (-2L)

• Handle up to 8 channels of SD/HD/3G-SDI streams (3 for the case of 3G-SDI) according to SMPTE2022-6
• Added new signal rx_vid_lock for each channel.
• Added new register axi_mm_addr_msb to control most significant 3 address bits of the 32-bit AXI memory map DDR access

• N/A

• N/A

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?

• Initial Release in ISE Design Suite 14.1

• Kintex-7
• Virtex-6 CXT/LXT/SXT/HXT

• ISE 14.1 software support
• Handle up to 6 channels of SD/HD/3G-SDI streams (3 for the case of 3G-SDI) according to SMPTE2022-6
• Per stream basis Forward Error Correction (FEC) in accordance to SMPTE2022-5
• Supports Level A and Level B FEC operations
• Supports block-aligned and non block-aligned FEC operations
• Supports Virtual Local Area Network (VLAN)
• AXI4-Stream data interfaces
• AXI4-Lite control interface
• Configurable channel selection based on IP source address, User Datagram Protocol (UDP) destination port, and Real-time Transport Protocol (RTP) Synchronization Source (SSRC) identifier over AXI4-Lite interface
• Supports SD-SDI, HD-SDI, 3G-SDI Level-A, 3G-SDI Level-B single stream and 3G-SDI Level-B dual stream

• N/A

• N/A

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