AR# 47210

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Video In to AXI4-Stream Core.

The following information is listed for each version of the core:

• New Features
• Bug Fixes
• Known Issues

LogiCORE IP Video In to AXI4-Stream Lounge:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/video_in_to_axi4_stream.html

Solution

General LogiCORE IP Video In to AXI4-StreamIssues

• N/A

LogiCORE IP Video In to AXI4-Stream v2.01.a

• Initial Release in ISE Design Suite 14.3, Vivado 2012.3

Supported Devices (ISE)

• All 7 series Devices
• All Virtex-6 Devices
• All Spartan-6 Devices

Supported Devices (Vivado)

• All 7 series Devices

New Features

•   - added "full-frame" feature. After reset, the first transaction on the AXI4S bus is the start-of-frame pixel.

Bug Fixes

• N/A

Known Issues

• (Xilinx Answer 53882) Why do I have a Video Format option for Bayer Sensor and Luma Only? 

LogiCORE IP Video In to AXI4-Stream v2.00.a

• Initial Release in ISE Design Suite 14.2, Vivado 2012.2

Supported Devices (ISE)

• All 7 series Devices
• All Virtex-6 Devices
• All Spartan-6 Devices

Supported Devices (Vivado)

• All 7 Series Devices

New Features

• Added support for Spartan6L and Artix-7L
• The names of the Verilog source code are changed to avoid namespace collisions
  

Bug Fixes

• N/A

Known Issues

• (Xilinx Answer 53882) Why do I have a Video Format option for Bayer Sensor and Luma Only? 

LogiCORE IP Video Into AXI4-Stream v1.0

• Initial Release in ISE Design Suite 14.1, Vivado 2012.1

Supported Devices (ISE)

• All 7 series Devices
• All Virtex-6 Devices
• All Spartan-6 Devices

Supported Devices (Vivado)

• All 7 series Devices

New Features

• ISE 14.1 software support
• Video (clocked parallel video data with synchronization signals - active video with either syncs, blanks or both) input
• AXI4-Stream Video Protocol interface for output
• Interface to Xilinx Video Timing Controller core for video timing generation
• Handles asynchronous clock boundary crossing between video clock domain and AXI4-Stream clock domain
• Selectable FIFO depth from 64 -8192 locations
• Selectable input data width of 8-64 bits

Bug Fixes

• N/A

Known Issues

• (Xilinx Answer 53882) Why do I have a Video Format option for Bayer Sensor and Luma Only? 

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