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  3. AR# 47211: LogiCORE IP AXI4-Stream to Video Out - Release Notes and Known Issues

AR# 47211

LogiCORE IP AXI4-Stream to Video Out - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP AXI4-Stream to Video Out Core.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues
LogiCORE IP AXI4-Stream to Video Out Lounge:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi4_stream_to_video_out.html

Solution

General LogiCORE IP AXI4-Stream to Video Out Issues

  • N/A

LogiCORE IP AXI4-Stream to Video Out v2.01.a

  • Initial release in ISE 14.3 and Vivado 2012.3 tools 

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 series

New Features

  •  Added "full-frame" feature.  After reset and lock, video output are enabled at the start of the vertical blanking period.

Bug Fixes

  • N/A

Known Issues

LogiCORE IP AXI4-Stream to Video Out v2.00.a

  • Initial release in ISE 14.2 and Vivado 2012.2 tools

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 series

New Features

  • Added support for master timing mode
  • Added support for Spartan-6L and Artix-7L
  • The names of the Verilog source code are changed to avoid namespace collisions

Bug Fixes

  • N/A

Known Issues

LogiCORE IP AXI4-Stream to Video Out v1.0

  • Initial release in ISE 14.1 and Vivado 2012.1 tools

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 series

New Features

  • ISE 14.1 design tools support
  • AXI4 Stream slave interface for input
  • Video (parallel video data, video syncs, and blanks) output
  • Interface to Xilinx Video Timing Controller core for video timing generation
  • Automatically synchronizes video timing to AXI4-Stream video
  • Handles asynchronous clock boundary crossing between AXI4-Stream clock domain and video clock domain
  • Selectable FIFO depth from 64 -8192 locations
  • Selectable data width for 8-64 bits

Bug Fixes

  • N/A

Known Issues

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
58410 AXI4-Stream to Video Out - Why is there no output from AXI4-Stream to the Video Out core? N/A N/A
AR# 47211
Date 11/10/2014
Status Archive
Type Release Notes
IP