We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47232

MIG 7 Series DDR3L - RESET# recommendations to meet JEDEC standard requirements


This answer record includes the specific RESET# guidelines that should be followed to ensure that JEDEC requirements (VIL/VIH = 20%/80%/VCCO) are met when using a DDR3L MIG 7 series FPGA design.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The guidelines are as follows:

  1. The RESET# pin is to use SSTL135.
  2. The SSTL135 signal to RESET# must not be terminated to Vtt (0.65V).
  3. The SSTL135 signal to RESET# must not use external pull-down resistor values stronger than 4.7K Ohms.

This information will be added to the 7 Series MIG User Guide (UG586).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34370 MIG DDR3 - JEDEC Specification; DDR3 SDRAM Reset Pin N/A N/A
AR# 47232
Date 02/01/2013
Status Active
Type Solution Center
  • MIG 7 Series