Description

This answer record includes the specific RESET# guidelines that should be followed to ensure that JEDEC requirements (VIL/VIH = 20%/80%/VCCO) are met when using a DDR3L MIG 7 series FPGA design.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The guidelines are as follows:

1. The RESET# pin is to use SSTL135.
2. The SSTL135 signal to RESET# must not be terminated to Vtt (0.65V).
3. The SSTL135 signal to RESET# must not use external pull-down resistor values stronger than 4.7K Ohms.

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