Description

This answer record includes the specific RESET# guidelines that should be followed to ensure that JEDEC requirements (VIL/VIH = 20%/80%/VCCO) are met when using a DDR3L MIG 7 series FPGA design.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).

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Solution

The guidelines are as follows:

1. The RESET# pin is to use SSTL135.
2. The SSTL135 signal to RESET# must not be terminated to Vtt (0.65V).
3. The SSTL135 signal to RESET# must not use external pull-down resistor values stronger than 4.7K Ohms.

This information will be added to the 7 Series MIG User Guide (UG586).

The VOH MIN of SSTL135 (VOH min = 0.825V) does not meet the VIH MIN for the RESET# (VIH MIN = 1.08V).

It is recommended to perform a pre and post layout simulation to ensure that the DRAM RESET# VIH MIN is met.

This guidance applies to MIG and PS memory controllers.

The following setup was used to simulate with SSTL135, SSTL15 and LVCMOS15.  

The appropriate VIH MIN is met with all drivers with all process corners. 

LVCMOS15 was run for completeness, SSTL135 and SSTL15 are recommended for driving the RESET# signal.

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