AR# 47265

LogiCORE IP DisplayPort v3.1 (Vivado 2012.1) - Why does Synthesis fail when the target language is set to VHDL?

Description

Why does Synthesis fail when the target language is set to VHDL?

Solution

This is a known issue caused by Vivado incorrectly generating the VHDL wrapper.

It does not properly tie off all of the optional ports, and this causes a failure in synthesis.

This issue is fixed in Displayport 3.2 in Vivado 2012.2.

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 47265
Date 08/18/2014
Status Archive
Type General Article
IP