AR# 47280


Virtex-6 Integrated Block for PCI Express v2.5 - Timing fails due to missing Block RAM Placement (LOC) Constraints in the Example Design UCF


Version Found: v2.5
Version Resolved and other Known Issues: see (Xilinx Answer 45723)

When Virtex-6 Integrated Block for PCI Express v2.5 core is generated for HX380T device in x8 Gen2 configuration, the example design UCF will not contain Block RAM LOC constraints.


The best way to fix this issue is to look up the PCIe block and logic locations in the PlanAhead tool and pick the closest block RAMs.

For PCIe block location X0Y0, the following constraints can be used:

INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_mem64" LOC = RAMB36_X5Y12;
INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_io_mem" LOC = RAMB36_X5Y13;
INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_mem_erom" LOC = RAMB36_X5Y14;
INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_mem32" LOC = RAMB36_X5Y15;

INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y0;
INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y1;
INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y2;
INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y3;

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
9/03/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A
AR# 47280
Date 01/21/2013
Status Active
Type General Article
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