We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47329

14.1 EDK, AXI Quad SPI - Does AXI Quad SPI core support AXI byte-wide accesses in XIP Mode?


Does AXI Quad SPI core support AXI byte access in XIP (eXecute In Place) Mode?

XIP mode is enabled with the parameter settings C_XIP_MODE = '1' and C_TYPE_OF_AXI4_INTERFACE = 1.


No, the AXI Quad SPI core does not support byte accesses when using the XIP interface feature.

This will be updated in a future datasheet release.
AR# 47329
Date 05/02/2012
Status Active
Type General Article
  • AXI Quad SPI
Page Bookmarked