AR# 47364: Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Example Design Simulation Timeout using Modelsim 10.1a
AR# 47364
Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Example Design Simulation Timeout using Modelsim 10.1a
Description
When using Mentor Graphics ModelSim 10.1a to simulate configurations of the Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper with the 1000BASE-X PCS/PMA physical interface and the 16-bit client interface, simulations may timeout with an error message such as: "ERROR: Simulation Running Forever" or "ERROR - Testbench timed out".
Solution
To work around this simulator issue, use Mentor Graphics ModelSim 6.6d, or a supported simulator from a different vendor.
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AR# 47364
Date
04/20/2012
Status
Active
Type
General Article
IP
Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper
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